• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.172-178
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• 1986

The recent interest in the design of filters is motivatied by the fact that such filter can be fully integrated using standard metal-oxide-semiconductor processing technology. This is due to replacing all the resistors in the active RC filter network by the switched capacitors. The voltage gain of a SC filter depends only on the rations of capacitance and these ratios can be obtained and maintained to high accuracy. Therefore, it is known that a switched capacitor is much better than a resistor in temperature and linearity characteristics. This paper proposed a programmable SC filter and proved the fact that ${omega}_0$ Q and G of this circuit can be controlled by digital signal. Experiments show that SC filter remains the low sensitivities but it can't avoid little influence of parasitic capacitance. As the transfer characteristic of the SC filter is varied with sampling frequency and resistor array, SC filtering technigue can be applied for digital processing, speech analysis and synthesis and so on.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.38-48
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• 2006

In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.103-106
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• 2001

본 논문은 radix-2 FFT를 파이프라인 기법으로 구현할때의 성능 향상을 위한 메모리 어드레싱기법에 대한 새로운 구조를 제안하고자 한다. Fast Fourier Transform(FFT) 프로세서의 속도 및 성능은 파이프라인 싸이클과 클럭에 좌우되므로, 동시에 병렬로 처리하기 위한 입력 데이타에 access 하기 위해 사용되어지는 기존의 메모리 어드레싱 기법은 지연문제로 인해 FFT 프로세서 성능 저하의 원인이 된다. 이 기법은 정확한 메모리 뱅크를 선택하기 위한 주소부 패러티 체크가 필요 없으므로 수행 속도를 빠르게 하고, ROM에 저장된 Coefficient의 실수부와 허수부의 상호교환특성을 이용하여 Coefficient ROM을 반으로 줄일 수 있다. 이 논문에서 제안된 구조는 VHDL을 사용하여 설계하였고, 설계된 회로를 시뮬레이션 및 합성시켰다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.176-179
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• 2000

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in current digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator systemfor for digital image.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.443-447
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• 2001

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in torrent digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator system for digital image.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.05c
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• pp.1-5
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• 2002

본 논문에서는 UART(Universal Asynchronous Receiver-Transmitter)를 soft IP(Intellectual Property) 모듈 형태로써 VLSI 설계과정을 통하여 구현하였다. 이 모듈은 현재 각종 통신 디바이스에서 최하 말단에서 직렬 데이터를 시스템으로 받아들이거나 병렬 데이터를 직렬 라인에 실어 보내는 중요한 역할을 담당한다. 본 연구에서 설계한 UART는 간단한 모듈 형태로 제작되어 있어 Verilog-HDL을 사용하여 직렬 송ㆍ수신을 필요로 하는 시스템에 내장되어 사용될 수 있다. 본 논문에서는 설계 순서에 따라 UART를 설계하고 Simulation을 하고 Synopsys Tool을 사용하여 Compile 과 Synthesis 후 Gate Area 와 Belay를 검출해 내었다. 합성결과 0.25$\mu$m 공정의 CMOS Cell Library를 사용하였을 경우 전체 면적은 1,013 gate가 나왔다. 본 논문에서 설계한 UART의 최장경로가 최대 4.12ns로 나타났으며, 최대 동작 클럭 주파수는 200MHz 로써 150Mbps 이상의 전송 속도를 가진다.