• Proceedings of the Korea Information Processing Society Conference
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• 2003.11b
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• pp.1085-1088
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• 2003

동기식 전송망에서는 다양한 동기클럭 성능과 상태가 나타날 수 있고, 이는 전송성능에 영향을 줄 수 있기 때문에 전송망 설계에 필요한 최대노드수의 변화가 생길 수 있다. 이에 따라 전송망에서 다양한 클럭성능과 상태를 적용할 수 있는 시뮬레이터가 요구된다. 따라서 본 논문에서는 전송망 동기클럭 시뮬레이터를 살펴보고, 또한 이를 이용하여 NE 노드에 따른 동기클럭 특성과 최대 노드수 결과를 얻었다. 본 연구 결과를 통해 볼 때 NE 노드의 성능보다 동기원의 성능이 최대 노드수에 미치는 영향이 크다는 것은 알 수 있었다.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.123-134
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• 2004

The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

• The KIPS Transactions:PartC
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• v.16C no.5
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• pp.637-644
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• 2009

A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.5
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• pp.487-491
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• 2008

This paper proposes the Byzantine fault tolerant clock synchronization scheme for wireless sensor networks to cope with the clock synchronization disturbance attack of malicious nodes. In the proposed scheme, a node which is requiring clock synchronization receives 3m+1 clock synchronization messages not only from its parent nodes but also from its sibling nodes in order to tolerate malicious attacks even if up to m malicious nodes exist among them. The results show that the proposed scheme is 7 times more resilient to the clock synchronization disturbance attack of malicious nodes than existing schemes in terms of synchronization accuracy.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.299-310
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• 2001

동기망과 동기식 전송망을 설계할 때에는 동기클럭의 단기안정 클럭특성과 이에 따른 망구성 노드수가 중요하게 고려되어야 할 사항이다. 또한 동기망과 전송망을 동시에 고려하여야 한다. 만일 전송망 만을 고려한다면 동기망에서의 발생할 수 있는 클럭성능 저하를 반영시킬 수 없기 때문이다. 지금까지의 연구는 주로 동기식 전송망만을 적용하여 연구되었다. 본 논문에서는 동기망과 동기식 전송망을 통합 고려하고, 최악의 원더생성을 적용하였을 때의 세가지 클럭상태에 따른 망동기클럭의 MTIE와 TDEV 특성을 얻었다. 또한 현 ITU-T 규격을 적용하여 세 가지 클럭상태에 따른 최대 망 구성 노드수를 구하였다.

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.49-57
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• 2009

The camera electronics in the KOMPSAT-3 payload provides the several control clocks in order to move the charges, which are converted from the light in the pixel, in the vertical and horizontal direction. Generally, the control clocks depend on the CCD internal design in the system. The KOMPSAT-3 payload uses the CCD controlled by 3-phase vertical clocks and 4-phase timing. The camera generates the various clocks such as the vertical clocks, the horizontal clocks, the summing clocks, the reset clocks and so on. The vertical clocks are deeply related to the camera performance and synchronized with satellite scan-rate even though they are relatively slow. Also, it gives the horizontal clocks without distortion under the very fast pixel-rate. This paper shows the design and simulation of the CCD clocks driver for the KOMPSAT-3 payload.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.141-147
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• 2005

Ding and Bhuyan, however, has shown that the performance of multistage interconnection networks(MIN's) can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an effective model for estimating the performance of multibuffered MIN's employing the approach is proposed. the relative effectiveness of the proposed model is identified compared to the traditional design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.327-332
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• 2012

In this paper, we analyzed the influence of different observation stations distributions on satellite clock offset estimation based on the PANDA software. The result shows that, when the distance between stations is shorter than 200km, the correlation of troposphere parameter and satellite clock offset parameter is strong, the accuracy of satellite clock offset estimation will be up to 0.8ns; when the distance between stations is up to 500km, as the correction of troposphere parameter and satellite clock offset parameter is significantly reduced, and the two kinds of parameters can be distinguished.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.10
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• pp.894-900
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• 2012

Indoor wireless positioning system uses ranging information of beacons in order to precisely estimate a tag location. To estimate distance between each beacons and tag, the system calculates arrival time of a tag pulse with clock of each beacon including independent clock offset. This clock offset seriously affects the performance of ranging and positioning. We propose in this paper a clock offset compensation method to solve this problem. To verify the performance of the proposed method, we simulated location estimation with random clock offset between -1,000ppm and 1,000ppm, and the result shows that the proposed scheme effectively solves the clock offset problem.