• KIPS Transactions on Computer and Communication Systems
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• v.3 no.12
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• pp.433-442
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• 2014

In this paper, we introduce the client side cache of distributed file system for enhancing read performance by eliminating the network latency and decreasing the back-end storage burden. This performance enhancement can expand the fields of distributed file system to not only cloud storage service but also high performance storage service. This paper shows that the distributed file system with client side SSD cache can satisfy the requirements of VDI(Virtual Desktop Infrastructure) storage. The experimental results show that full-clone is more than 2 times faster and boot time is more than 3 times faster than NFS.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.156-159
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• 2015

최근 콘텐츠 전송 네트워크(content delivery network, CDN)와 클라우드 컴퓨팅(cloud computing)을 결합하여 효과적으로 콘텐츠를 전달하기 위한 방법이 대두되고 있으며 이와 같이 클라우드 컴퓨팅과 결합하여 서비스되는 CDN을 클라우드 CDN 이라고 칭한다. 본 논문에서는 클라우드 CDN 환경에서의 효과적인 가상 머신 (virtual machine, VM) 관리를 위한 캐시서버(caching server)로써의 VM의 네트워크 I/O 성능 분석을 다룬다. 해당 성능 분석은 엔드 유저(end-user)들과 캐시서버 간 동영상 스트리밍(streaming)을 통하여 이루어졌으며 해당 캐시 서버의 네트워크 I/O 성능에 영향을 주는 다양한 경우에 대하여 진행되었다. 본 논문에서의 성능 분석은 클라우드 CDN 환경에서의 데이터센터(datacenter) 선택 및 요청 라우팅(routing) 등에 적용될 수 있다.

• KIISE Transactions on Computing Practices
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• v.22 no.6
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• pp.278-283
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• 2016

Due to explosive increase in the amount of data produced recently, cloud storage system is required to offer high and stable performance. However, VM (Virtual Machine) migration may result in lowered storage service performance. Especially, in an environment where the host-side flash cache is used in a cloud system, the existing warmed up cache is lost and the problematic cold start begins at a new cache due to a VM migration. In this paper, we first demonstrate and analyze the cold start problem and then propose Cachemior (Cache migrator) which enables efficient hot start of the flash cache.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.8
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• pp.768-772
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• 2008

Today's microprocessor normally includes several processing cores to reduce the energy consumption without losing performance. In this paper, data transfer ordering mechanism can be efficiently used for cache coherence solution in unidirectional ring interconnect. RING-DATA ORDER combines the simplicity of GREEDY-ORDER and the performance of RING-ORDER. RING-DATA ORDER can be easily applicable to multicore processor with unidirectional ring interconnect.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.11
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• pp.836-852
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• 2006

This paper proposes an L1 cache prefetch scheme using an excessively aggressive hardware prefetcher and a hardware prefetch filter having a small direct-mapped filtering cache. A quantitative analysis method has been introduced and applied to analyze nonideal effects of aggressive cache prefetching. From those analysis results, the structure and algorithm of a prefetch filter has been derived and simulated, and the overall system performance has been measured using a cycle-by-cycle cache simulator. Experimental results show that the proposed scheme improves the overall system performance by 18% on the average over several benchmarks

• The KIPS Transactions:PartA
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• v.12A no.3 s.93
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• pp.215-222
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• 2005

The efficient utilization of cache memories is a key factor in achieving high performance for computing large signal transforms. Nonunit stride access in computation of large DFTs causes cache conflict misses, thereby resulting in poor cache performance. It leads to a severe degradation in overall performance. In this paper, we propose a dynamic data layout approach considering the memory hierarchy system. In our approach, data reorganization is performed between computation stages to reduce the number of cache misses. Also, we develop an efficient search algorithm to determine the optimal tree with the minimum execution time among possible factorization trees considering the size of DFTs and the data access stride. Our approach is applied to compute the fast Fourier Transform (FFT). Experiments were performed on Pentium 4, $Athlon^{TM}$ 64, Alpha 21264, UtraSPARC III. Experiment results show that our FFT achieve performance improvement of up to 3.37 times better than the previous FFT packages.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

• The Journal of the Korea Contents Association
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• v.14 no.10
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• pp.20-31
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• 2014

Recently, cache sharing methods have been studied in order to effectively reply to user requests in mobile P2P networks. In this paper, we propose a cache sharing scheme based on a cluster considering the peer connectivity in mobile P2P networks. The proposed scheme shares caches by making a cluster that consists of peers preserving the connectivity among them for a long time. The proposed scheme reduces data duplication to efficiently use the cache space in a cluster. The cache space is divided into two parts with a data cache and a temporary cache for a cache space. It is possible to reduce the delay time when the cluster topology is changed or the cache data is replaced utilizing a temporary cache. The proposed scheme checks the caches of peers in a route to a cluster header and the caches of one-hop peers in order to reduce the communication cost. It is shown through performance evaluation that the proposed scheme outperforms the existing schemes.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.421-423
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• 2002

동영상 정보 검색 시스템은 비교적 작은 크기의 동영상 클립과 클립을 인덱싱하기 위한 키 프레임으로 구성된다. 본 논문에서는 동영상 정보 검색 시스템을 위한 버퍼 캐시에서 버퍼 교체 기법을 연구하였고, 버퍼 캐시 사용의 효율성을 연구하였다. 실험을 통해 버퍼 캐시가 좋은 성능을 가지려면 적은 수의 동영상 클립에 요청이 편중되어야 함을 알 수 있었다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.1
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• pp.68-80
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• 2000

The modern software technology toward modularization has changed the cache accessing behavior dramatically. Many modern operating systems are also departing from the past monolithic structure toward the highly modularized structure referred to as microkernel. Microkernel-based operating systems are more portable and extensible, but are likely to have worse performance. This paper quantitatively analyzes the effect of microkernel structure on cache memory to identify the primary factor for its performance degradation. Through the experiment performed on a Intel Pentium Pro processor platform, we found that the microkernel structure suffers from remarkably higher misses for L1, L2 cache and TLB than the monolithic one does. We also found that the performance of a microkernel is more dependent on the efficiency of cache memory than IPC. Finally, we found that these results come from the effect of frequent context switches mainly caused by the structural feature of a microkernel.