• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.473-486
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• 2004

NUMA systems have remote access caches(RAC) in each local node to reduce the overhead for repeated remote memory accesses. By this RAC, memory latency and network traffic can be reduced and the performance of the multiprocessor system can be improved. Until now, several cache replacement policies have been proposed in recent years, and there also is cache replacement policy for multiprocessor systems. In this paper, we propose a cache replacement policy which is based on cache line coherence information. In this policy, the cache line that does not have an ownership is replaced first with respect to cache line that has an ownership. Like this way, the overhead to transfer ownership is avoided and the memory latency can be decreased. We also propose “Keeping-Ownership replacement policy with MRU (KOM)” and “Keeping-Ownership replacement policy with Reference Bit(KORB)” to reduce the frequent replacement penalty of the ownership-lacking cache line. We compare and analyze these with LRU and Pseudo LRU(PLRU). The simulation shows that KOM outperforms the PLRU by 25%, and KORB outperforms the PLRU by 13%. Although the hardware cost of KOM is very small, the performance of KOM is nearly equal to that of the LRU.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.343-345
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• 2014

플래시 메모리의 인기가 증가하면서 스토리지 시스템의 변화를 가져왔다. 플래시 메모리 기반의 SSD(Solid State Disk)는 기존의 HDD(Hard Disk Drive)를 대체할 매체로 주목을 받고 있으며 HDD에 비해 훨씬 더 높은 대역폭, 랜덤 접근 성능 및 충격에 강한 장점들을 갖는다. 그러나 플래시 메모리는 HDD와 달리 덮어쓰기(In-Place update)가 불가능 하기 때문에, 데이터를 업데이트 하기 위해서는 해당영역을 지운 후 업데이트를 해야 하는 단점이 있다. 본 논문에서는 캐시 안에서의 거의 접근하지 않을 블락과 캐시로 들어가는 것을 막기 위한 기법을 제시한다. 이것은 캐시의 오염을 막고 더 오랜 기간 동안 캐시 안에서 인기 있는 블락 들을 유지하고 높은 히트율로 연결될 것이다. 또한 캐시 교체의 수를 줄임으로써 SSD의 쓰기를 감소할 것이고 그 결과 성능 뿐만 아니라 SSD의 수명도 연장 에도 도움이 될 것이다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.133-135
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• 2003

최근 인터넷 기반 서비스 환경의 질적개선과 이에 따른 이용자 증가에 따라. 오디오나 동영상과 같은 규모가 크고 동적 특성을 가진 웹 컨텐츠의 수가 증가하는 추세이다. 이에 따라 'hit ratio' 뿐만 아니라 오브젝트의 크기를 기반으로 하는 'byte hit ratio' 또한 캐시 성능을 평가하는 중요한 측정 요소가 되었다. 이러한 측정기준을 대상으로 할 때, 기존의 웹 캐시 교체 정책중 HP연구소의 GDSF (Greedy-Dual-Size with Frequency)알고리즘과 LFU-DA(LFU with Dynamic Aging)알고리즘이 우수한 성능을 보이는 것으로 알려져있는데, 이러한 기존의 웹 캐시 교체 정책은 서버와의 네트워크 상태를 고려하지 않은 정책이고, 이에 따라 네트워크 상태에 따른 전송비용의 차이를 반영하지 못하고 있다. 따라서 본 논문에서는 서버와 웹 캐시 간의 네트워크 상태를 반영할 수 있는 캐시 교체 정책을 제안하고, 이에 대한 실험을 수행하였으며, 그 결과 사용자의 요구에 대한 응답시간의 감소 효과를 얻을 수 있었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.399-410
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• 2002

Web cache, which is functionally another word of proxy server, is located between client and server. Web cache has a limited storage area although it has broad bandwidth between client and proxy server, which are usually connected through LAN. Because of limited storage capacity, existing objects in web cache can be deleted for new objects by some rules called replacement algorithm. Hit rate and byte-hit rate are general metrics to evaluate replacement algorithms. Most of the replacement algorithms do satisfy only one metric, or sometimes none of them. In this paper, we propose two replacement algorithms to achieve both high hit rate and byte-hit rate with great satisfaction. In the first algorithm, the cache is appropriately partitioned according to file types as a basic model. In the second algorithm, the cache is composed of two levels; the upper level cache is managed by the basic algorithm, but the lower level is collectively used for all types of files as a shared area. To show the performance of the proposed algorithms, we evaluate hit rate and byte-hit rate of the proposed replacement algorithms using the trace driven simulation.

• Journal of Korea Spatial Information System Society
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• v.6 no.1 s.11
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• pp.19-29
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• 2004

Recently, studies have been performed to improve the cache performance of the R-Tree in main memory. A general mothed to improve the cache performance of the R-Tree is to reduce size of an entry so that a node can store more entries and fanout of it can increase. However, this method generally requites additional process to reduce information of entries and do not support incremental updates. In addition, the cache miss always occurs on moving between a parent node and a child node. To solve these problems efficiently, this paper proposes and evaluates the PR-Tree that is an extended R-Tree indexing method using prefetching in main memory. The PR-Tree can produce a wider node to optimize prefetching without additional modifications on the R-Tree. Moreover, the PR-Tree reduces cache miss rates that occur in moving between a parent node and a child node. In our simulation, the search performance, the update performance, and the node split performance of the PR-Tree improve up to 38%. 30%, and 67% respectively, compared with the original R-Tree.

• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.87-94
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• 2003

As the number of the Internet users increases explosively, a solution for this problem is web caching. So, many techniques on improving cache server performance have been suggested. In this paper, we analyze the cause of the bottleneck in cache servers, and propose an arbitral thread and delayed caching mechanism as a solution. We use an arbitral thread in order to provide a quick service to user requests through eliminating the ready multi-thread search problem in case of disk writing operation. We also use delayed caching in order to provide stable system operation through avoiding overloaded disk operation and queue threshold. Proposed cache server is implemented through modification on SQUlD cache server, and we compare its performance with the original SQUID cache server.

• Journal of KIISE
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• v.42 no.1
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• pp.107-113
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• 2015

In a database system, updates on pages that are made by a transaction should be stored in a secondary storage before the commit is complete. Generic secondary storages have volatile DRAM caches to hide long latency for non-volatile media. However, as logs that are only written to the volatile DRAM cache don't ensure durability, logging latency cannot be hidden. Recently, a flash SSD with capacitor-backed DRAM cache was developed to overcome the shortcoming. Storage devices, like those with a non-volatile cache, will increase transaction throughput because transactions can commit as soon as the logs reach the cache. In this paper, we analyzed performance in terms of transaction throughput when the SSD with capacitor-backed DRAM cache was used as log storage. The transaction throughput can be improved over three times, by committing right after storing the logs to the DRAM cache, rather than to a secondary storage device. Also, we showed that it could acquire over 73% of the ideal logging performance with proper tuning.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.50-56
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• 2000

In this paper, for improving the speed of query processing on distributed directory system, we proposed a caching mechanism which is store the queries and their on the remote site objects in the cache of local site. For this, first, cached information which is stored in distributed directory systems is classified as application data and system data. And cache system architecture is designed according to classified information. Second least-TTL replacement mechanism which uses the weighted value of geographical information and access frequency for replacements are developed for each cache. Finally, performance evaluations are performed by comparing the proposed caching mechanism and other mechanisms (LRU, LFU replacement). Our least-TTL mechanism shows a performance improvement of 25% over the LRU and that of 30% over LFU.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.608-616
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• 2005

A cache architecture is proposed here which evokes prefetch at level 1 cache miss. Existing structures only prefetch at level 2 cache miss. In the proposed cache architecture, level 1 cache miss would select demand fetch block and prefetch block from the level 2 cache and store to level 1 cache and prefetch cache, respectively. According to an experimental analysis using 11 benchmark programs, the hierarchical cache architecture that employs both a level 1 cache prefetcher and a level 2 cache prefetcher obtained a maximum $19\%$ increased performance when compared to the cache architecture that employs only a level 2 cache prefetcher.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.11a
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• pp.143-146
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• 2003

본 논문에서는 미디어 프로세서에서 메모리 참조시 평균 메모리 참조 지연시간을 줄이기 위하여 지역성이 높으나 재사용성이 떨어지는 미디어 데이터를 지역성과 재사용성이 높은 일반 데이터로부터 분리하여 별도의 캐시에 저장하도록 하는 캐시 구조를 제안하였다. 또한, 미디어 데이터의 선인출 기법을 캐시 운영 전략으로 채택하도록 하여 평균 메모리 지연시간을 단축하였다. EPIC, JPEG 벤치마크에 대한 실험결과, 미디어 데이터를 일반 데이터 캐시와 구분한 이중캐시 구조가 하나의 캐시에 모든 데이터를 저장하는 단일캐시구조에 비하여 캐시미스횟수가 감소하였음을 확인할 수 있었다.