• Journal of Korea Spatial Information System Society
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• v.6 no.1 s.11
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• pp.3-17
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• 2004

With the rapid growth of the Internet geographic information services through the WWW such as a location-based service and so on. Web GISs (Geographic Information Systems) have also come to be a cluster-based architecture like most other information systems. That is, in order to guarntee high quality of geographic information service without regard to the rapid growth of the number of users, web GISs need cluster-based architecture that will be cost-effective and have high availability and scalability. This paper proposes the design of the cluster-based web GIS with high availability and scalability. For this, each node within a cluster-based web GIS consists of main memory spatial databases which accomplish role of caching by using data declustering and the locality of spatial query. Not only simple region queries but also the proposed system processed spatial join queries effectively. Compare to the existing method. Parallel R-tree spatial join for a shared-Nothing architecture, the result of simulation experiments represents that the proposed spatial join method achieves improvement of performance respectively 23% and 30% as data quantity and nodes of cluster become large.

• Journal of the Korea Society of Computer and Information
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• v.20 no.4
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• pp.1-10
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• 2015

NAND flash systems require deletion operation and do not support in-place update, so the storage systems should use Flash Translation Layer (FTL). However, there are a lot of memory consumptions using mapping table in the FTL, so recently, many studies have been proposed to resolve mapping table overhead. These studies try to solve update propagation problem in the nand flash system which does not use mapping table. In this paper, we present a novel index structure, called CL-Tree(Cache List Tree), to solve the update propagation problem. The proposed index structure reduces write operations which occur for an update propagation, and it has a good performance for search operation because it uses multi-list structure. In experimental evaluation, we show that our scheme yields about 173% and 179% improvement in insertion speed and search speed, respectively, compared to traditional B+tree and other works.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.1098-1105
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• 1999

The caches in distributed shared memory systems enhance the performance by reducing memory access latency and communication overhead, but they must solve the cache coherence problem. This paper proposes a new directory protocol to solve the cache coherence problem and to improve the system performance in distributed shared memory systems. To maintain the cache coherence of shared data, processors within a limited distance reduce the communication overhead by using a bit-vector like the full directory scheme. Processors over a limited distance store pointers in a directory pool. Since the bit-vector and the directory pool remove the unnecessary cache invalidations, the proposed scheme reduces the communication traffic and improves the system performance. The dynamic limited directory scheme reduces the communication traffic up to 66 percents compared with the limited directory scheme and the number of directory access up to 27 percents compared with the dynamic pointer allocation scheme.

• Journal of KIISE
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• v.42 no.9
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• pp.1109-1116
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• 2015

In this paper, we propose a query processing approach that uses the Spark functional programming and distributed memory system to solve the computational overhead of SPARQL. In the semantic web, RDF ontology data is produced at large scale, and the main challenge for the semantic web is to query and manipulate such a large ontology with a high throughput. The most existing studies on SPARQL have focused on deploying the Hadoop MapReduce framework, and although approaches based on Hadoop MapReduce have shown promising results, they achieve a low level of throughput due to the underlying distributed file processes. Therefore, in order to speed up the query processes, we suggest query- processing methods that are based on memory caching in distributed memory system. Our approach is also integrated with a clause unification method for propagating between the clauses that exploits Spark join, map and filter methods along with caching. In our experiments, we have achieved a high level of performance relative to other approaches. In particular, our performance was nearly similar to that of Sempala, which has been considered to be the fastest query processing system.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.6
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• pp.849-861
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• 1995

In this paper, a new trace driven simulation algorithm is proposed to evaluate the bus traffic and the miss ration of the various sector cache memories, which have various sub-block sizes and block sizes and associativities and number of sets, with a single pass through an address trace. Trace-driven simulaton is usually used as a method for performance evaluation of sector cache memories, but it spends a lot of simulation time for simulating the diverse cache configurations with a long address trace. The proposed algorithm shortens the simulation time by evaluating the performance of the various sector cache configurations. which have various sub-block sizes and block sizes and associativities and number of sets , with a single pass through an address trace. Our simulation results show that the run times of the proposed simulation algorithm can be considerably reduced than those of existing simulation algorithms, when the proposed algorithm is miplemented in C language and the address traces obtained from the various sample programs are used as a input of trace-driven simulation.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.6
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• pp.353-359
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• 2016

In this paper, we propose a high performance L1 cache structure for the high clock CPU. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to reduce miss ratio, and a way-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is stored into the two-way set associative buffer. For the high performance and fast access time, we propose an one way among two ways set associative buffer is selectively accessed based on the way-select table (WST). According to simulation results, access time can be reduced by about 7% and 40% comparing with a direct cache and Intel i7-6700 with two times more space respectively.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.2
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• pp.236-246
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• 1999

최근 운영체제 개발분야에서 마이크로커널 설계 기술이 새로운 경향으로 부각되고 있다. 마이크로커널은 기존의 모노리딕 커널과 상이한 구조를 가지고 있으므로, 성능분석 튜닝을 위하여 새로운 도구를 필요로 한다. 본 논문에서는 마이크로커널 기반 운영체제를 위한 성능 측정도구 MKperf의 개발에 관하여 기술하고자 한다. MLperf 는 마이크로커널 r조의 성능에 중요한 영향을 미치는 문맥 교환과 원격 프로시저 호출을 추적할수 있다. 뿐만 아니라 , 캐시와 TLB와 같이 메모리 성능에 결정적인 영향을 미치는 다양한 하드웨어 성능요소들을 측정할수 있다. MDperf 의 이러한 측정 기능은 마이크로커널 기반 운영체제 성능을 정량적으로 분석하는데에 유용하게 사용될 수있다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.625-627
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• 2004

최근 들어 인터넷의 발달과 더불어 PDA, 핸드폰과 같은 모바일 디바이스와 다양한 정보가전용 기기들에 네트워크 기반의 자바기술이 적용되고 있으며, 이러한 자바 기술을 사용함으로써 플랫폼 독립성 이식성, 보안성, 이동성 둥의 장점을 얻을 수 있다. 그러나, 자바로 작성된 응용프로그램은 C, C++로 작성된 응용프로그램 보다 수행속도가 느리다는 단점이 있다. 이러한 문제점을 해결하기 위해서는 자바가상머신의 성능향상이 필수적이다. 지금까지 메모리 관리를 위한 가비지 컬렉션, 소프트웨어나 하드웨어를 이용한 바이트 코드 변환, 인라인캐시(inline-cache)를 사용한 접근 속도 향상 등 많은 부분에서 활발한 연구가 진행되고 있다. 본 논문에서는 모바일 플랫폼에서 동작하는 KVM(kilo-virtual machine)의 성능향상을 위한 쓰레드 구조를 분석하고 설계한다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10c
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• pp.706-708
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• 2002

3차원 텍스쳐 기반의 볼륨 렌더링 기법은 추가적인 하드웨어가 필요 없기 때문에 개발비용이 적다는 장점이 있지만 다각형 기반 렌더링에 최적화 된 범용 그래픽 하드웨어를 그대로 사용하기 때문에 성능이 낮다는 단점이 있다. 이에 본 논문에서는 병렬 구조의 고성능 볼륨 렌더링 시스템에서 사용되던 볼륨 정보 분한 기법을 범용 그래픽 하드웨어에 적용하는 새로운 3차원 텍스쳐 기반 볼륨 그래픽 구조를 제안한다. 제안하는 구조를 통해 볼륨 정보를 분할하여 처리하면, 번용 그래픽 하드웨어가 갖고 있던 물리적 메모리 크기의 한계성을 극복할 수 있다. 또한 전체 해상도의 알파 블렌딩이 아닌 분할된 볼륨 정보 하나가 차지하는 크기만큼의 작은 해상도로 알파 블렌딩을 수행함으로서 렌더링 단계와 프레임 버퍼간의 데이터 전송량을 1/30로 줄이고 픽셀 캐시의 적중률을 99.9%에 근접하게 높일 수 있다.