• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Journal of English Language & Literature
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• v.55 no.2
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• pp.337-357
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• 2009

Ned Kelly, the bushranger, is a legendary figure of special significance to the Australians of today. The Aussies' affection for this "horse thief" derives from the fact that the latter has become a national ideal of the "battler" who does not give up in the face of hardships. Peter Carey's is considered to be one of the "national narratives" that not only heroize but also give voice to the Irish rebels who fought for "fair go" in the colonial Australia. However, this paper asserts that there are more to the novel than merely paying a tribute to the national icon, especially when the novel is examined in the context of the "republic controversy." In 1999, the preceding year of the novel's publication, Australia had a national referendum on the issue of whether or not to secede from the Commonwealth. Due to the procedural manipulation of the royalist ruling party, republicanism was voted down. At the time when the majority of Australians were irate with the result of the referendum, Carey's retelling of the supposedly anti-British rebel failed to promote the lost cause. This paper investigates how the narrativization of the legendary figure, whose anti-British and anti-authoritarian attitude can be easily translated into the cause of republicanism, came to appeal to the general reading public. In so doing, this paper compares Carey's novel with the historical Kelly's two epistles: Jerilderie and Cameron Letter. This comparison brings to light what is left out in the process of Carey's narrativization of the rebel's life: the subversive militant voice of an Irish nationalist. The conclusion of this paper is that the possibility for Kelly's life to surface again in the 21st century as a sort of counter-memory is contained by Carey through its inclusion in a highly personalized domestic narrative.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.29-39
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• 2007

RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1478-1481
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• 2010

기존의 테마파크에 RFID를 이용하면 보다 편리하게 출입관리를 할 수 있고, 카드 한 장으로 테마파크 내에서 결제부터 부대시설과 서비스까지 이용할 수 있다. 이러한 모델은 이미 서브원 곤지암리조트 스키장과 캐리비언베이 워터파크 등 에서 도입하여 사용하고 있다[1][2]. 그러나 RFID를 이용한 유비쿼터스 모델들의 공통적인 단점은 RFID 카드 사용에 대한 피드백을 받을 수 없다는 것이다. 다시 말해서 RFID 카드에 대한 정보를 사용자는 모르기 때문에 자신이 RFID 카드로 무엇을 얼마나 결제했는지, 어떠한 서비스를 사용했는지 다시 확인할 수 없다는 문제점이 있다. 본 논문에서는 이러한 기존의 시스템에 스마트폰을 이용하여 사용자와 테마파크를 유기적으로 연결시켜줌으로써, 스마트폰을 통해 자신의 결제정보, 서비스 이용내역 등을 실시간으로 확인 가능할 수 있는 u-테마파크 모델을 제시한다. u-테마파크 모델을 이용하면 스마트폰을 통해 부대시설(놀이공원의 놀이기구, 스키장의 리프트 등)의 대기시간을 실시간으로 확인할 수 있고, RFID 카드를 소지한 일행의 위치를 찾을 수 있으며, 테마파크의 모든 이용객들과 정보를 교환할 수 있는 SNS(Social Network Service)등의 새로운 서비스를 제공할 수 있다. 테마파크 측에서는 실시간으로 취합되는 고객정보를 이용하여 이용률이 떨어지는 고객들의 특징을 파악해 해당 고객들에게 맞는 서비스를 제공하고 맞춤 마케팅을 하는 등의 체계적인 관리를 할 수 있어 다양한 마케팅과 새로운 서비스 제공이 가능하다는 이점이 있다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.5
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• pp.16-26
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• 2001

In this paper, we present a new scheduling method called CDSS(Carried-Dependence Self-Scheduling) for efficiently execution of the loop with intra dependency between iterations based on the central queue. We also implemented it on shared memory system using Java language. Also, we study the modification that converts the existing self-scheduling method based on the central task queue for parallel loops onto the same form applied to loop with loop-carried dependences. The proposed method is self scheduling and assigns the loops in three-level considering the synchronization point according to the dependence distance of the loops. To adapt the proposed scheme and modified methods into various platforms, including a uni-processor system, we use threads for implementation. Compared to other assignment algorithms with various changes of application and system parameters, CDSS is found to be more efficient than other methods in overall execution time including scheduling overheads. CDSS shows improved performance over modified SS, Factoring, GSS and CSS by about 0.02, 40.5, 46.1 and 53.6%, respectively. In CDSS, we achieve the best performance on varying application programs using a few threads, which equal the dependence distance.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.37-47
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• 2016

The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.

• Korean Journal of Applied Biomechanics
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• v.19 no.4
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• pp.779-791
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• 2009

The purpose of this study is to develop a program that computes the position of the instantaneous center of rotation while an object moves in a circular motion. For this study, a mathematical algorithm was developed and implemented on the experimental data. Data for pitching (40m carry) and putting (4m) strokes were obtained from a skilled female golfer. A computer program (Centering 1.0) calculated the experimental data and found the radius of the instantaneous center of rotation. When the data were taken broadly, the program produced an error distance of radius. When the data were divided gradually, the program produced a very close instantaneous center of rotation. On comparing pitching and putting strokes, putting was found to have a greater radius than pitching. The instantaneous centers of rotation of putting were not in the golfer's body rather, they were 3m away from the club head. The Centering 1.0 program can calculate the instantaneous center of rotation with at least three sets of experimental data.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.21-28
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• 2017

Practical models for FPGA architectures which include performance- and/or density-enhancing components such as carry chains, wide function multiplexers, and memory/multiplier blocks are being applied to academic FPGA placement tools which used to rely on simple imaginary models. Previously the techniques such as pre-packing and multi-layer density analysis are proposed to remedy issues related to such practical models, and the wire length is effectively minimized during initial analytic placement. Since timing should be optimized rather than wire length, most previous work takes into account the timing constraints. However, instead of the initial analytic placement, the timing-driven techniques are mostly applied to subsequent steps such as placement legalization and iterative improvement. This paper incorporates the timing driven techniques, which check if the placement meets the timing constraints given in the standard SDC format, and minimize the detected violations, with the existing analytic placer which implements pre-packing and multi-layer density analysis. First of all, a static timing analyzer has been used to check the timing of the wire-length minimized placement results. In order to minimize the detected violations, a function to minimize the largest arrival time at end points is added to the objective function of the analytic placer. Since each clock has a different period, the function is proposed to be evaluated for each clock, and added to the objective function. Since this function can unnecessarily reduce the unviolated paths, a new function which calculates and minimizes the largest negative slack at end points is also proposed, and compared. Since the existing legalization which is non-timing driven is used before the timing analysis, any improvement on timing is entirely due to the functions added to the objective function. The experiments on twelve industrial examples show that the minimum arrival time function improves the worst negative slack by 15% on average whereas the minimum worst negative slack function improves the negative slacks by additional 6% on average.

• Journal of Popular Narrative
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• v.25 no.1
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• pp.429-462
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• 2019

This paper argues how the concept of melodrama can be articulated with the Affect Theory and Posthumanism in relation to animal or environment representation which have emerged as the new topics of the recent era. The argument will be made through the discussion of Agustin Zarzosa's book, Refiguring Melodrama in Film and Television: Captitve Affects, Elastic Sufferings, Vicarious Objects. Using a genealogical approach, the book revisits the notion of mode, affect, suffering (hysteria), and excess which have been dealt with in the existing studies of melodrama. In chapter one, he broadens the concept of melodrama as a mode into the means of redistribution of suffering across the whole society in the mechanism of the duo of evil and virtue. It is the opposition of Brooks's argument in which melodrama functions as the means of proving the distinction between evil and virtue. Chapter two focuses on the fact that melodrama is an elastic system of specification rather than a system of signification, with the perspective of Deleuzian metaphysics. Through the analysis of Home from the Hill (Vincente Minnelli, 1959), this chapter pays attention to an 'affect' generated by the encounters between the bodies and the Mise-en-Scène as a flow not of a meaning but of an affect. Chapter three argues that melodrama should reveal an unloved (woman's) suffering, opposing the discussion on the role of melodrama as the recovery of moral order. Safe (Todd Haynes, 1995), dealing with female suffering caused by the industrial and social environment, elaborates on the arguments on melodrama in relation to female hysteria with ecocritical standpoints. The rest of the two chapters discusses the role of melodrama for the limitation and extension of the notion of the human through 'animal' and 'posthuman' melodrama. It argues that the concept of melodrama as 'excess' and 'sacrifice' blurs the boundary between human and inhuman. In summary, although the author Zarzosa partly agrees with Peter Brook's notion of mode, affect and sufferings,he elaborates the concept of melodrama, by articulating philosophical arguments such as Deleuzianism, feminism, and posthumanism (Akira Lippit and Carry Wolf) with the melodrama. Thefore, Zarzosa challenges the concepts of melodrama led by Brooks, which had been canonical in the field.