• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.53-58
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• 2008

In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.61-71
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• 1999

The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.6
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• pp.11-17
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• 2001

Design and implementation of the MAC protocol processor prototype for high speed wireless LAN, which has interface with 5GHz OFDM PHY layer, is presented. We analyze the IEEE 802.11 MAC protocol specification and then separate the MAC protocol functions to be implemented by hardware and firmware and define the interface in which frames can be exchanged. That is, it is considered that high speed queue processing and interfaces with RISC processor and OFDM PHY layer. Protocol control and transmission/reception functions of the MAC functions are implemented in hardware in order to guarantee high speed processing in MAC layer. The developed MAC hardware block operates at 10MHz main clock. Therefore, transmission rate in PHY layer is about 80Mbps because data transmission/reception between MAC layer and PHY layer is performed as unit of octet. The designed FPGA MAC function chip has been implemented in wireless LAN test board and it is verified that DCF function is operated correctly.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.362-370
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• 2010

In this paper, a compact RF Front-end module for Wireless Fidelity(Wi-Fi) and Worldwide Interoperability for Microwave Access(WiMAX) applications is realized by low temperature co-fired ceramic(LTCC) technology. The RF Front-end module is composed of three LTCC band-pass filters, a Film Bulk Acoustic Resonator(FBAR) filter, fully embedded matching circuits, an SPDT switch for mode selection, an SPDT switch for Tx/Rx selection, and an SP4T switch for band selection. The parasitic elements of 0.2~0.3 pF are generated by the structure of stacking in the top pad pattern for DC block capacitor of SPDT switch for mode selection. These kinds of parasitic elements break the matching characteristic, and thus, the overall electrical performance of the module is degraded. In order to compensate it, we insert a parallel lumped-element inductor on capacitor pad pattern for DC block, so that we obtain the optimized performance of the RF Front-end module. The fabricated RF front-end module has 12 layers including three inner grounds and it occupies less than $6.0mm{\times}6.0mm{\times}0.728mm$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.4
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• pp.716-722
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• 2017

In this paper, a fully printed NFC tag operating at 13.56 MHz was designed and fabricated using silver nano-paste and carbon ink. The proposed NFC tag has a printed coil with an inductance of $2.74{\mu}H$ on a PI film for application to an NFC tag IC with an internal capacitance of 50 pF. Screen printing technology used in this paper has advantages such as large area printing for mass production, low cost and eco-friendly process compared to conventional PCB manufacturing process. The proposed structure consists of a circular coil implemented as a single layer using silver nano-paste and carbon ink, a jumper pattern for chip mounting between the outer edge and the center of the coil, and an insulation pattern between the coil and the jumper pattern. In order to verify the performance of the proposed NFC tag, we performed the measurements of the printing line width, thickness, line resistance, adhesion and environmental reliability, and confirmed the suitability of the NFC tag based on the full-printed manufacturing method.