• Title/Summary/Keyword: 칩형태

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Trends in Rapid Detection Methods for Food-borne pathogenic Microorganisms by Using New Technologies (신기술 이용 식중독균 신속검출법 개발 동향 분석)

  • Kim, Hyun-Joo;Kim, Yong-Soo;Chung, Myung-Sub;Oh, Deog-Hwan;Chun, Hyang-Sook;Ha, Sang-Do
    • Journal of Food Hygiene and Safety
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    • v.25 no.4
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    • pp.376-387
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    • 2010
  • Recently, speedy, convenient and easy detection technologies have been developed rapidly and on the contrary, studies on development of traditional detectors applying biochemical characteristics has gradually been decreased. This review examined trend in current studies on detection of food-borne pathogenic microorganisms in the fields of selective media, immuno-assay, Polymerase Chain Reaction (PCR), microarray, terahertz spectroscopy & imagination and so on. Most traditional methods to detect the organisms from food matrix rely on selective media and such a method have disadvantages like long time requirement and distinguishing one species only from each selective medium although they are highly economical. Various new convenient methods such as Enzyme Linked Immuno-sorbent Assay (ELISA), paper-strip kit, fluoroimmunoassay etc. have been developed. The most ideal method for detecting food-borne pathogenic microorganisms in foods should be accurate, convenient, rapid and economical. Additionally, it is needed that capabilities of quantitative analysis and automation to be applied to industries.

Design and Evaluation of a Microcomputer-based Vacuum Drying System for Shiitake Mushrooms (마이크로컴퓨터 시스템을 이용한 표고버섯의 감압건조에 대한 연구)

  • Choi, Jae-Yong;Kim, Kong-Hwan;Chun, Jae-Kun
    • Korean Journal of Food Science and Technology
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    • v.19 no.6
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    • pp.550-555
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    • 1987
  • Strain gauges attached on the Bourdon tube and load cell were used as the sensors for measuring the vacuum pressure in drying chamber and the weight loss of Shiitake mushrooms respectively. The vacuum drying system was interfaced further with the Bear II microcomputer. The interface devices used were built with such IC chips as MC 6821, ADC 0809, SN 74244 and SN 7424. The relationship between readings of vacuum gauge (P, mmHg) and digital outputs (D) from the microcomputer was represented by P =3.08 D-13.4875(r=0.9999). The weights of drying sample (W) were also related with the digital outputs (D) by W=0.4076 D-6.4762 (r=0.9999). During the vacuum drying of Shiitake mushrooms. the data on pressure and weight were recorded at regular intervals using an acquisition program on the microcomputer system. The Page model was fitted well to the drying data of Shiitake mushrooms. resulting in the following empirical equations : $(M-M_e)/(M_o-M_e)=\exp(-0.1569t^{1.0048})$ at 400 mm Hg up to 14 hours and $(M-M_e)/(M_o-M_e)=\exp(-0.1385_t^{1.2688})$ at 600 mm Hg up to 8 hours.

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Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache (코어와 L2 캐쉬의 수직적 배치 관계에 따른 3차원 멀티코어 프로세서의 온도 분석)

  • Son, Dong-Oh;Ahn, Jin-Woo;Park, Jae-Hyung;Kim, Jong-Myon;Kim, Cheol-Hong
    • Journal of the Korea Society of Computer and Information
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    • v.16 no.6
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    • pp.1-10
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    • 2011
  • In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

마이크로볼로미터 IR 소자의 응답도 특성의 진공도 의존성 연구

  • Han, Myeong-Su;Han, Seok-Man;Sin, Jae-Cheol;Go, Hang-Ju;Kim, Hyo-Jin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.361-361
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    • 2013
  • 비냉각 적외선 검출소자는 빛이 전혀 없는 환경에서도 사물을 감지하는 열상장비의 핵심소자이다. 마이크로볼로미터 적외선 검출기는 상온에서 동작하며, 온도안정화를 위해 TEC를 장착하여 진공패키지로 조립된다. 패키지는 진공을 유지할 수 있도록 일반적으로 메탈로 제작되며, 단가 감소 및 생산성 증대를 위해 wafer level packaging 방법을 이용한다. 마이크로볼로미터의 특성은 패키지의 진공 변화에 매우 민감하다. 센서의 감도를 증가시키기 위해서는 진공환경을 유지해야 한다. 볼로미터 소자의 특성은 상압에서 열전도는 기판과 멤브레인 사이의 에어갭을 통해 열손실을 야기하므로 센서의 반응도가 현저히 줄어든다. 에어갭이 1 um 정도 되더라도 그 사이에 존재하는 열전도가 가능하므로 진공을 유지하여 열고립 상태를 증대시킬 수 있다. 이에 본 연구에서는 소자의 동작시 압력, 즉 진공도가 볼로미터 소자의 반응도 특성에 미치는 영향을 조사하였다. 마이크로볼로미터 소자는 $2{\times}8$ 어레이 형태로 제작하였으며, metal pad를 각 단위셀에 배치하였으며, 공통전극으로 한 개의 metal pad를 넣어 설계하였다. 흡수체로써 VOx를 사용하였으며, 열 고립구조를 위해 2.5 um 공명 흡수층의 floating 구조로 멤브레인을 형성하였다. 진공패키지는 메탈패키지를 제작하여 볼로미터 칩을 TEC 위에 장착하였으며, 신호의 감지를 위해 가변저항을 매칭시켰다. 반응도는 신호 대 잡음 값을 획득하여 소자에 도달하는 적외선 에너지에 대해 반응하는 값을 계산에 의해 얻어내는 것이다. 픽셀 크기는 $50{\times}50$ um이며, 패키지 조립 공정 후 온도변화에 따른 저항 측정을 통해 TCR 값을 얻었다. 이때 TCR은 약 -2.5%/K으로 나타났다. $2{\times}8$의 4개 단위소자에 대해 측정한 값은 균일하게 TCR 값이 나타났다. 광반응 특성은 볼로미터 단위소자에 대해서 먼저 고진공(5e-6 torr) 하에서 측정하였으며, 반응도는 25,000 V/W의 값을 나타내었고, 탐지도는 약 2e+8 $cmHz_{1/2}$/W로 나타났다. 패키지의 압력 조절을 위해 TMP 및 로터리 펌프를 이용하여 100 torr에서 1e-4 torr의 범위에서 압력조절 밸브를 이용하여 질소가스의 압력으로 진공도를 변화시켰다. 적외선 반응신호는 압력이 증가함에 따라 감소하였으며, 2e-1 torr의 압력에서 신호의 크기가 감소하기 시작하여 5 torr에서 반응도의 1/2 값을 나타냄을 알 수 있었다. 30 torr 이상에서는 신호가 잡음값 과거의 동일하여 신호대 잡음비가 1로 나타남을 알 수 있었다. 또한 진공도 변화에 대해, 흑체온도에 따른 반응도 및 탐지도의 특성을 조사한 결과를 발표한다. 반응도의 증가를 위해 진공도는 진공도는 1e-2 torr 이하의 압력을 유지해야 함을 본 실험을 통해 알 수 있었다.

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Low-Power Motion Estimator Architecture for Deep Sub-Micron Multimedia SoC (Deep Submicron 공정의 멀티미디어 SoC를 위한 저전력 움직임 추정기 아키텍쳐)

  • 연규성;전치훈;황태진;이성수;위재경
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.95-104
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    • 2004
  • This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

Implementation of LDPC Decoder using High-speed Algorithms in Standard of Wireless LAN (무선 랜 규격에서의 고속 알고리즘을 이용한 LDPC 복호기 구현)

  • Kim, Chul-Seung;Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.12
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    • pp.2783-2790
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    • 2010
  • In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.

Double-Gauss Optical System Design with Fixed Magnification and Image Surface Independent of Object Distance (물체거리가 변하여도 배율과 상면이 고정되는 이중 가우스 광학계의 설계)

  • Ryu, Jae Myung;Ryu, Chang Ho;Kim, Kang Min;Kim, Byoung Young;Ju, Yun Jae;Jo, Jae Heung
    • Korean Journal of Optics and Photonics
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    • v.29 no.1
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    • pp.19-27
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    • 2018
  • A change in object distance would generally change the magnification of an optical system. In this paper, we have proposed and designed a double-Gauss optical system with a fixed magnification and image surface regardless of any change in object distance, according to moving the lens groups a little bit to the front and rear of the stop, independently parallel to the direction of the optical axis. By maintaining a constant size of image formation in spite of various object-distance changes in a projection system such as a head-up display (HUD) or head-mounted display (HMD), we can prevent the field of view from changing while focusing in an HUD or HMD. Also, to check precisely the state of the wiring that connects semiconductor chips and IC circuit boards, we can keep the magnification of the optical system constant, even when the object distance changes due to vertical movement along the optical axis of a testing device. Additionally, if we use this double-Gauss optical system as a vision system in the testing process of lots of electronic boards in a manufacturing system, since we can systematically eliminate additional image processing for visual enhancement of image quality, we can dramatically reduce the testing time for a fast test process. Also, the Gaussian bracket method was used to find the moving distance of each group, to achieve the desired specifications and fix magnification and image surface simultaneously. After the initial design, the optimization of the optical system was performed using the Synopsys optical design software.

Comparative analysis of the digital circuit designing ability of ChatGPT (ChatGPT을 활용한 디지털회로 설계 능력에 대한 비교 분석)

  • Kihun Nam
    • The Journal of the Convergence on Culture Technology
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    • v.9 no.6
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    • pp.967-971
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    • 2023
  • Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.

Treatment of Animal Wastewater Using Woodchip Trickling Filter System and Physical and Microbial Characteristics of Wood Chip Media (목편살수여상조를 이용한 축산뇨오수 처리와 목편여재의 물성 및 부착미생물 특성)

  • Ryoo, Jong-Won
    • Journal of Animal Environmental Science
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    • v.17 no.2
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    • pp.71-80
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    • 2011
  • Trickling filter has been extensively studied for the domestic wastewater treatment especially for the small scale plants in rural area. The purpose of this research is to survey the physical and microbial characteristics of wood chip media and the removal efficiency of animal wastewater using wood chip trickling filter system. The trickling filtration system comprises a filtration bed packed with wood chip media having a particle dia. of 5~7cm. The method comprises natural air from the bottom of the bed. The system also comprises a control mechanism including a time a constant discharge pump for controlling supply of the wastewater into the bed. The following conclusions were obtained from the results of this research. 1. The specific surface area of wood chip was 0.4123 $m^2$/g, pore volume was 0.0947 $cm^3$/g, density was 0.49 g/$cm^3$. It has forms of parallelogram and oblong which have numerous small pore space. This wood chip has been good condition for microorganism's habitat, having very larger specific surface area by complex the three dimension structure of cellulose at wood's major ingredients. 2. The total counts of in attached aerobic microbes were ranged from $10^6$ to $10^8$ CFU/g, and anaerobes microbial numbers were from $10^4$ to $10^7$. The aerobic microbial numbers appeared to be much more than those of anaerobic microbial numbers. 3. The average efficiency of $BOD_5$ and CODcr were 74.5% and 51.5%, respectively. The removal efficiency of T-N and T-P were 61.4%, 56.2%, respectively. But SS removal levels remain 19.3%.

The Trend of Aviation Terrorism in the 4th Industrial Revolution Period and the Development Direction for Domestic Counter Terrorism of Aviation (제4차 산업혁명 시대의 항공 테러리즘 양상 및 국내 항공테러 대응체계 발전방향)

  • Hwang, Ho-Won;Kim, Seung-Woo
    • The Korean Journal of Air & Space Law and Policy
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    • v.32 no.2
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    • pp.155-188
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    • 2017
  • On the one hand, the 4th Industrial Revolution provides a positive opportunity to build a new civilization paradigm for mankind. However, on the other hand, due to the 4th Industrial Revolution, artificial intelligence such as 'Goggle Alpha Go' revolutionized and even the human ability was replaced with a 'Silicon Chip' as the opportunity to communicate decreases, the existence of human beings is weakened. And there is a growing concern that the number of violent crimes, such as psychopath, which hunts humans as games, will increase. Moreover, recent international terrorism is being developed in a form similar to 'Psychopathic Violent-Crime' that indiscriminately attacks innocent people. So, the probability that terrorist organizations abuse the positive effects provided by the Fourth Industrial Revolution as means of terrorism is increasing. Therefore, the paradigm of aviation terrorism is expected to change in a way that attacks airport facilities and users rather than aircraft. Because airport facilities are crowded, and psychopathic terrorists are easily accessible. From this point of view, our counter terrorism system of aviation has many weak points in various aspects such as: (1) limitations of counter-terrorism center (2) inefficient on-site command and control system (3) separated organization for aviation security consultation (4) dispersed information collection function in government (5) vulnerable to cyber attack (6) lack of international cooperation network for aviation terrorism. Consequently, it is necessary to improve the domestic counter terrorism system of aviation so as to preemptively respond to the international terrorism. This study propose the following measures to improve the aviation security system by (1) create 'Aviation Special Judicial Police' (2) revise the anti-terrorism law and aviation security law (3) Strengthening the ability respond to terrorism in cyberspace (4) building an international cooperation network for aviation terrorism.

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