• The KIPS Transactions:PartA
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• v.15A no.5
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• pp.259-268
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• 2008

Multi-Core processors have become main-stream microprocessors in recent years. Servers based on these multi-core processors are widely adopted in High Performance Computing (HPC) and commercial business applications as well. These servers provide increased level of parallelism, thus can potentially boost the performance for applications. However, the shared resources among multiple cores on the same chip can become hot spots and act as performance bottlenecks. Therefore it is essential to optimize the use of shared resources for high performance and scalability for the multi-core servers. In this paper, we conduct experimental studies to analyze the positive and negative effects of the resource sharing on the performance of HPC applications. Through the analyses we also characterize the performance of multi-core servers.

• Journal of the Korean Institute of Gas
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• v.24 no.5
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• pp.20-28
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• 2020

In this study, the damage impact range in the case of a hydrofluoric acid leak accident was predicted using formula calculation, impact assessment simulations, and CFD simulations, and the results were compared and analyzed with the actual environmental impact report. Formula calculation was performed by using the leak source model and diffusion model. Impact assessment simulation was performed by KORA provided by the Korean Ministry of Environment, ALOHA by the United States Ministry of Environment, and PHAST, which is relatively widely used among commercialization programs, and the STAD-CMM+program for CFD simulation. Was utilized. Considering convenience, speed, acceptability, and economics from the user's perspective, ALOHA and KORA were the most appropriate methods for predicting the impact of hydrofluoric acid leakage. In addition, the results of this study will help to reduce unnecessary regulations in the process of government policy development and optimize the investment in the safety field of the company, effectively utilizing the limited resources of the government and the company.

• Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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• v.12 no.4
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• pp.335-344
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• 2014

The safety case program has been prepared for the development of the disposal facility of low- and intermediate-level radioactive waste in Korea. For the development of the radioactive waste disposal facility, this program can be applied for the safety demonstration of the facility and for the safety judgment of development step based on the international standards and domestic development environment. Systematic safety approach of this program includes the safety strategies such as optimization, robustness, demonstrability and defense-in-depth principle which are based on the safety principle and objectives. From the quality of assessment basis, safety arguments focused on the uncertainty management and the confidence building can assure the disposal safety during the step-wise safety assessment.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.5
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• pp.350-354
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• 2009

To optimize the performance of software programs, it is important to know certain hardware parameters such as the CPU speed, the cache size, the number of TLB entries, and the parameters of the memory subsystem. There exist several ways to obtain the values of various hardware parameters. Firstly. the values can be taken from the hardware manual. Secondly, the parameters can be obtained by calling functions provided by the operating systems. Finally, hardware detection programs can find the desired values. Such programs are usually executed on PC or server systems and report the CPU speed, the cache size, the number of TLB entries, and so on. However, they do not sufficiently detect the parameters of one of the most important parts of the computer concerning performance, namely the memory bank layout in the memory subsystem. In this paper, we present an algorithm to detect the memory bank parameters. We run an implementation of our algorithm on various embedded systems and compare the detected values with the real hardware parameters. The results show that the presented algorithm detects the cache size, the number of TLB entries, and the memory bank layout with high accuracy.

• Journal of the Society of Naval Architects of Korea
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• v.39 no.1
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• pp.73-81
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• 2002

This study is performed to evaluate and design the vibration characteristics of the onboard machinery with resilient mountings. To reduce the vibration revel of onboard machinery with resilient mountings, it is important to evaluate and, if necessary modify vibration characteristics of the resilient mountings. In this study we have developed a program to calculate natural frequencies of the machinery with resilient mountings, forced vibration levels due to internal excitation force of the machinery itself and external excitation forces of the main engine and the propeller, and the force and motion transmissibility of the resilient mountings. The developed program can be also applied to optimal design of the resilient mountings for obtaining a target natural frequency and for achieving a minimum forced vibration level at the center of gravity of the machinery.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.687-691
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• 2011

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory in consideration of EM (electro-migration) and eFuse resistance variation based on a $0.18{\mu}m$ generic process, which is used for an analog trimming application. First, we use an external program voltage to increase the program power applied an eFuse. Secondly, we apply a scheme of precharging BL to VSS prior to RWL (read word line) activation and optimize read NMOS transistors to reduce the read current flowing through a non-programmed cell. Thirdly, we design a sensing margin test circuit with a variable pull-up load out of consideration for the eFuse resistance variation of a programmed eFuse. Finally, we increase program yield of eFuse OTP memory by splitting the length of an eFuse link.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.197-206
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• 2002

Many researchers have been interested in the optimization of parallel programs through the latency hiding by overlapping the communication with the computation. We ana1yzed overlapping effects in the circular shift communication which is one of the collective communications being frequently used In many data parallel programs. We measured the time which can be possibly overlapped and the time which cannot be overlapped in over all circular shift communication period on an Ethernet switch-based clustered system. The result from each platform nay be used for the input of optimizing compilers. The previous performance models usually have two kinds of drawbacks one is only based on point-to-point communication, so it is not appropriate for analyzing the overall effects of collective communications. The other provides the performance of collective communication, but no overlapping effect. In this paper we extended the previous models and analyzed the experimental results of the extended model.

• Journal of Digital Contents Society
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• v.17 no.4
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• pp.257-263
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• 2016

Cable drum schedule is the final step for the electrical equipment of the power plant, and is assigned cables to efficiently cable drum. In this paper, we have implemented an automated program which cables are scheduled in accordance with the capacity of the cable drum for each cable code. Proposed cable drum schedule was applied to the dynamic programming algorithm to effectively solve the optimization problem, and the implemented program is conducted so as to verify the proposed model. The experiment results show that implemented program eliminates the errors that can occur existing method, so we were able to reduce the design time of cable drum schedule. Cables for the electrical equipment of the power plant is designed to at least 2 million units or more. Thus the automation program to provide applies, it is considered that the design time of the cable drum schedule can be greatly reduced without serious error.

• Journal of KIISE:Software and Applications
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• v.35 no.5
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• pp.281-287
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• 2008

Data transfers occur during the execution time of a Java program, from constant to variable, from variable to other variable and so on. Data are located in memory and hence data transfer requires access to memory. As memory access generates both time delay and energy consumption it is absolutely necessary to know the data transfer overheads incurred among different paths not only to write an efficient program but also to build a high-performance Java virtual machine. In this paper we classify Java memory into three different regions, constant, local variable, and field, and then investigate data transfer overheads among these regions. The result says that the transfer between local variables incur the least overhead usually, while the transfer between fields incur the most. The difference of overheads reaches up to a double. Optimization techniques like JIT reduces the data transfer overhead dramatically. It is observed that the overhead is reduced from 14 to 27 times for the case of Hotspot JVM.

• The Transactions of the Korea Information Processing Society
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• v.5 no.5
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• pp.1172-1184
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• 1998

ILP(Instruction Level Parallelism) processors use code reordering algorithms to expose parallelism in a given sequential program. When applied to a loop, this algorithm produces a software-pipelined loop. In a software-pipelined loop, each iteration contains a sequence of parallel instructions that are composed of data-independent instructions collected across from several iterations. For vector loops, however the software pipelining technique can not expose the maximum parallelism because it schedules the program based only on data-dependencies. This paper proposes to schedule differently for vector loops. We develop an algorithm to detect vector loops at object code level and suggest a new vector scheduling algorithm for them. Our vector scheduling improves the performance because it can schedule not only based on data-dependencies but on loop structure or iteration conditions at the object code level. We compare the resulting schedules with those by software-pipelining techniques in the aspect of performance.