• Annual Conference of KIPS
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• 2017.04a
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• pp.1131-1134
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• 2017

본 연구는 차동 용량형 섬유 압력 센서를 개발하고, 이를 깔창에 부착하여 보행 측정에 응용하는 것을 목적으로 한다. 차동 용량형 섬유 압력 센서는 3장의 전도성 섬유 사이에 2장의 절연체를 위치시키는 형태로, $5cm{\times}5cm{\times}0.23cm$ (가로 ${\times}$ 세로 ${\times}$ 두께) 크기로 제작하였다. 커패시턴스를 측정하기 위해 커패시턴스-디지털 변환칩(AD7152), ATMega328로 구성된 시스템을 제작하였고 PC로 데이터를 전송하여 모니터링을 수행하였다. 센서의 힘-커패시턴스 변화 특성 평가를 위해 센서에 가하는 중량을 65 kg 까지 5 kg 씩 증가시켜 가며 커패시턴스 변화를 측정하였다. 실험 결과, 무게에 따라 커패시턴스가 증가하는 것을 확인하였다. 보행 측정 가능성을 평가하기 위해 센서를 깔창에 부착한 후 보행 신호를 측정하였으며, 그 결과 보행에 따라 센서의 커패시턴스 값이 변화하는 것을 확인하였다. 이로부터 제작한 차동용량형 섬유 센서는 보행 측정에 활용할 수 있는 가능성을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.62-71
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• 2002

An intergral C-V converter is proposed to solve the nonlinearity problem of capacitive pressure sensors. The integral C-V converter consists of a switched-capacitor integrator and a switched-capacitor differential amplifier. It converts the sensor capacitance change which is inversely proportional to an applied pressure into a linear voltage output. Various PSPICE simulations prove that the convertor has excellent characteristics, such as low nonlinearity less than 0.01%/FS and low sensitivity to parallel offset capacitance and parasitic capacitance for the displacement range of sensor diaphragm set to 0 ${\sim}$ 90% of the initial distance between the electrodes in the simulation. We also show that the offset compensation and the gain trimming are easily achieved with the integral C-V converter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.654-657
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• 2000

In the winding system, the constant tension control is too important. In this study, we've used a variable PID system as a function of a radius of winding roll. As a result, it was possible to measure a winding roll radius in the real time by making a mathematical model for measuring a winding roll radius. Finally, we've compared PID parameters as a function of winding roll radius after getting PID parameters in terms of the Ziegler & Nichols(ZN) method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.86-93
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• 2008

A low-power, low-noise, highly-linear hybrid balun circuit is proposed for 2.4-GHz fully differential CMOS direct conversion receivers. The hybrid balun is composed of a passive transformer and loss-compensating auxiliary amplifiers. Design issues regarding the optimal signal splitting and coupling between the transformer and compensating amplifiers are discussed. Implemented in $0.18{\mu}m$ CMOS process, the 2.4 GHz hybrid balun achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart and +23 dBm of IIP3 only at a current consumption of 0.67 mA from 1.2 V supply. It is also examined that the hybrid balun can remarkably lower the total noise figure of a 2.4 GHz fully differential RF receiver only at a cost of 0.82 mW additional power dissipation.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.125-126
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• 2008

A differential capacitance deviation-to-time converter for interfacing position sensor is presented. It consists of triaxial position sensor, six comparators, six current mirrors, and control logic. The prototype differential capacitance deviation-to-time interval converter has been simulated using Chartered $0.35-{\mu}m$ CMOS parameters. The simulation results show that the maximum conversion time of the converter is $350{\mu}s$ and the linearity error is less than ${\pm}0.00l5%$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1254-1260
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• 2009

CDMA tele-Controller system is designed with a low power consumption 8 bit microcontroller, ATmega 2560. ATmega 2560 microcontroller consists of 4 UART (Universal asynchronous receiver/transmitter) ports, 4 kbytes EEPROM, 256 kbytes flash memory, 4 kbytes SRAM. 4 URAT is used for CDMA modem, communication for GPS module, EEPROM is used for saving a configuration for program running, a flash memory of 256 kbytes is used for storing a F/W(Firm Ware), and SRAM is used for stack, storing memory of global variables while program running. We have tested the communication distance between the coast station and sea by the fabricated control board using 800 MHz CDMA modem and GPS module, which is building for the navigational aid management system by remote control. As a results, the receiving signal strength is above -80 dBm, and then the characteristics of the control board implemented more than 10 km in the distance of the communication.