• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4A
• /
• pp.519-527
• /
• 2000

This paper suggests and analyzes the Serially Concatenated Space-Time Code(SCSTC) with the possibility of a efficient high-speed transmission in a band limited channel. The suggested code has a structure that uses the interleaver to connect the space-time code as an inner code and the convolutional code as a outer code serially. This code keeps the advantage of high-speed transmission and also has the high BER performance. The performance of the suggested system is compared with the conventional bandwidth efficient trellis coded modulation, such as a Serially Concatenated Trellis Coded Modulation (SCTCM) and a Turbo-Trellis Coded Modulation(Turbo-TCM). The results show that the suggested system has a 2.8dB and 3dB better BER performance than SCTCM and Turbo-TCM respectively in case of the transmission rate 2b/s/Hz in fading channel.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.15 no.4
• /
• pp.230-236
• /
• 2022

In this paper, we propose an efficient concatenated code for both random and ISI errors on diffusion-based molecular communication channels. The proposed concatenated code was constructed by combining the ISI-mitigating code designed for ISI mitigation and the ISI-Hamming code strong against random errors, and the BER(bit error rate) performance was analyzed through simulation. In the case of the above M=1,200 channel environment, it was found that the error rate performance of the concatenated code follows the error rate performance of the ISI-mitigating code, which is strong against ISI, and follows the error rate performance of the ISI-Hamming code, which is strong against random errors, in the channel environment below M=600. In M=600~1,200, the concatenated code shows the best error rate performance among those of three codes, which is analyzed because it can correct both random errors and errors caused by ISI. In the following cases of below M=800, it can be seen that the error rate of the concatenated code and the ISI-mitigating code shows an error rate difference of about 1.0×10^-1 on average.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.4C
• /
• pp.337-342
• /
• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.255-258
• /
• 2004

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only Partial-sum block in the hardware.

• Proceedings of the KIEE Conference
• /
• 2002.07d
• /
• pp.2463-2465
• /
• 2002

본 논문에서는 Home Automation을 위한 하드웨어와 제어용 프로그램의 개발에 목적을 두었다. Home Automation에 쓰인 하드웨어 부분에서는 8051 마이크로 컨트롤러를 사용했다. 본 논문에서 가장 중요한 부분은 플랜트끼리의 통신 알고리즘이며, 일반 가정용 IBM PC의 USB 포트를 이용한 화상 전달방법이다. 화상 전달에 필요한 DLL부분은 C++로 제작되었으며 전체적인 제어용 프로그램은 비주얼툴인 Visual Basic으로 제작하였다. 하드웨어는 각각의 플랜트에 따라 각각의 구동부가 있으며 몇몇 구동부에는 다중 통신을 위한 8051 마이크로 프로세서가 있다. 이 모든 장치의 데이터 흐름을 알 수 있도록 PC를 통해 디스플레이하며 PC와 직렬 통신을 통해 이 모든 것이 이루어진다.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.9 no.1
• /
• pp.39-45
• /
• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Proceedings of the KIPE Conference
• /
• 2004.07a
• /
• pp.374-379
• /
• 2004

H-브릿지 멀티레벨 인버터는 여러 개의 단상 Power Cell을 직렬로 연결함으로써 저전압 전력용 반도체를 사용하여 고전압을 얻을 수 있고, 정현파에 가까운 출력전압 파형을 얻을 수 있는 멀티레벨 인버터 토폴로지이다. 본 토폴로지는 출력전압 레벨에 비례하여 Power Cell의 수가 증가하므로, 주제어기의 연산능력에 대한 부담증가와 신호선의 많아지는 단점이 있다. 따라서 Power Cell제어를 직접적인 PWM 신호가 아닌 통신을 사용함으로써 이러한 단점을 극복할수 있으며, 신뢰성 측면이나 보수/유지 측면에서도 유리하다. 본 논문은 산업현장에서 신뢰성을 인정받아 많이 사용되고 있는 직렬통신 방식의 일종인 CAN통신 인터럽터를 이용한 H-브릿지 멀티레벨 인버터 Power Cell의 PWM 동기화 및 위상 전이 방법에 관한 것이다. 제안된 방법의 주요 장점은 주제어기와 셀 제어기 사이에 직렬통신(CAN)을 사용함으로써 주제어기와 셀 제어기의 신호선의 단순화, 주제어기의 부담 감소, Power Cell의 모듈화, 셀 단위의 보호동작 용이, 확장성 향상 그리고 제어 신호 및 Power Cell의 신뢰성을 향상에 있다. 13레벨로 구성된 H-브릿지 멀티레벨 인버터 시험을 통해 제안된 방법의 타당성과 신뢰성을 입증하였다.

• Proceedings of the KIPE Conference
• /
• 2019.07a
• /
• pp.311-312
• /
• 2019

본 논문에서는 직렬-직렬(SS) 보상 구조를 가지는 양방향 무선전력전송 시스템의 비통신 전력전송 제어 방법에 대해 소개한다. 또한 2차단에서의 전력 전달 제어에 1차단의 위상의 필요함을 보이며, 이를 도출하기 위한 20kHz 전류 센싱 방법에 대해서 다룬다. 시뮬레이션과 실험 파형을 통해 소개한 제어 변수와 고주파수 전류 신호 센싱의 방법의 타당성을 증명하였다.

• Proceedings of the Korea Society of Information Technology Applications Conference
• /
• 2003.06a
• /
• pp.81-82
• /
• 2003

• Journal of Convergence for Information Technology
• /
• v.7 no.6
• /
• pp.173-179
• /
• 2017

Recently, with the development of IoT, there have been increasing cases of transmitting and receiving data by connecting more than one devices supporting various communication methods. In this paper, we propose a multi-terminal emulator supporting various communication methods. The system supports multiple channel connections for each communication method, schedules data transmission, collects communication statistics, represents them into graphs, and stores log records. By using this system, it is possible to test the communication connection between multiple devices, and it is expected to provide convenience for IoT system development.