• Title/Summary/Keyword: 지연& #40;Delay& #41; 모델

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A Design Method of a Completion Signal Generation Circuit of Memory for Asynchronous System (비동기식 시스템을 위한 메모리의 동작 완료 신호 생성 회로)

  • 서준영;이제훈;조경록
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.10
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    • pp.105-113
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    • 2004
  • This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.