• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.354-356
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• 2013

본 논문에서는 CMOS 스위치를 이용한 디지털 이득 제어 구조를 가진 이득 조절 증폭기 (PGA, Programmable Gain Amplifier)를 제안한다. 기존의 아날로그 이득 제어 방식에서는 가변적인 트랜스 컨덕턴스를 활용하는 과정에서 바이어스 전류나 전압에 의해 이득이 변하게 되어 순간적으로 구성회로의 바이어스 포인트가 변하기 때문에 왜곡이 발생하게 되는 문제점이 있다. 본 논문에서는 이러한 문제점을 해결하기 위해 기존의 gm-boosting 증폭기를 변형한 디지털 이득 제어 방식으로 설계되어 있기 때문에 우수한 선형성을 가지며 특수 목적에 맞도록 그 이득을 6dB에서 60dB까지 7가지 단계로 조절 가능하다. 제안한 PGA는 기존 회로에 비해 0.2dB 보다 작은 이득오차와 0.47mW의 낮은 소비전력 특성을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6A
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• pp.697-704
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• 2004

This paper describes the design and fabrication of an MMIC variable gain LNA for 5GHz wireless LAN applications, using 0.5${\mu}{\textrm}{m}$ gate length GaAs MESFET transistors. The advantages of high gain and low noise performance of E-MESFETS and excellent linear performance of D-MESFETS are combined as a cascode topology in this design. Behavioral model equations are derived from the MESFET nonlinear current voltage characteristics by using Turlington's asymptote method in a cascode configuration. Using the behavioral model equations, a 4${\times}$50${\mu}{\textrm}{m}$ E-MESFET as a common source amplifier and a 2${\times}$50${\mu}{\textrm}{m}$ D-MESFET as a common gate amplifier are determined for the cascode amplifier. The fabricated variable gain LNA shows a noise figure of 2.4dB, variable gain range of more than 17dB, IIP3 of -4.8dBm at 4.9GHz, and power consumption of 12.8mW.

• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

• Journal of Advanced Navigation Technology
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• v.13 no.1
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• pp.48-53
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• 2009

The CMOS RF front-end for Global Positioning System(GPS)are implemented in 1P8M CMOS $0.13{\mu}m$ process. The LNAs consist of LNA1 with high gain and low NF, and LNA2 with low gain and high IIP3 for supporting operation with active and passive antenna. the measured performances of both LNAs are 16.4/13.8 dB gain, 1.4/1.68 dB NF, and -8/-4.4 dBm IIP3 with 3.2/2 mA form 1.2 V supply, respectively. The quadrature downconversion mixer is followed by transimpedance amplifier with gain controllability from 27.5 to 41 dB. The front-end performances in LNA1 mode are 39.8 dB conversion gain, 2.2 dB NF, and -33.4 dBm IIP3 with 6.6 mW power consumption.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2570-2572
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• 2001

본 논문에서는 저주파 신호 증폭기에서 DC 이득에 의해 앰프가 포화되는 것을 막기 위해 필요한 큰 커플링 커패시터와 바이어스 저항의 면적을 줄이기 위한 회로를 제안한다. 또한, 이 경우 연산증폭기의 양 입력 단에 연결되는 바이어스 저항과 앰프의 이득을 설정하기 위해 사용되는 저항사이의 큰 값의 차이로 인해 발생하는 오프셋을 줄이기 위해 적절한 기준 전압을 정의하는 방법을 소개한다. 제안된 회로를 사용했을 때, 기존의 저항으로 앰프의 입력단을 바이어스할 때의 한계인 오프셋의 문제를 해결함으로써 보다 최적화된 면적으로 설계가 가능했다. 이 기법을 적외선 리모콘 수신 IC의 앰프에 적용했을 때, 커플링 커패시터와 바이어스 저항으로 설정되는 -3dB 주파수를 3kHz에 설정한 경우, 저항과 커패시터가 차지하던 면적의 12%를 차지했다.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.4
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• pp.48-53
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• 2001

A three-stage low noise amplifier(LNA) for the Base-station of the IMT-2000 is designed and implemented. In the first stage, a GaAs HJt-FET which has good noise characteristics is made use of. Monolithic microwave integrated circuits(MMICS) are used in the second and the third stage to achieve both the high gain and high output power. Although the balanced amplifier is used to reduce the input VSWR, it is done only in the first stage because we have to minimize the noise figure attributed to the phase difference of the balanced amplifier. It is shown that the implemented LNA has the gai over 39.74dB, the gain flatness less than ±0.4dB, the noise figure below 0.97dB, input and output VSWRs less than 1.2, and OIP₃(output third order intercept point) of 38.17dBm in the operating frequency range.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.569-577
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• 1999

A wideband RF receiver for satellite mobile communications system was fabricated and evaluated of performance in low noise amplifier and high gain amplifier. The low noise amplifier used to the resistive decoupling and self-bias circuits. The low noise amplifier is fabricated with both the RF circuits and the self-bias circuits. Using a INA-03184, the high gain amplifier consists of matched amplifier type. The active bias circuitry can be used to provide temperature stability without requiring the large voltage drop or relatively high-dissipated power needed with a bias stabilized resistor. The bandpass filter was used to reduce a spurious level. As a result, the characteristics of the receiver implemented here show more than 55 dB in gain, 50.83 dBc in a spurious level and less than 1.8 : 1 in input and output voltage standing wave ratio(VSWR), especially the carrier to noise ratio is a 43.15 dB/Hz at a 1 KHz from 1537.5 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.1045-1049
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• 2010

In this paper, we proposed an ultra-low power low noise amplifier(LNA) using a TSMC 0.18 ${\mu}m$ RF CMOS process. To satisfy the low power consumption with high gain, a current-reused technique is utilized. In addition, a low bias voltage in the subthreshold region is utilized to achieve ultra low power characteristic. The designed LNA has the voltage gain of 13.8 dB and noise figure(NF) of 3.4 dB at 2.4 GHz. The total power consumption of the designed LNA is only 0.63 mW from 0.9 V supply voltage and chip occupies $1.1\;mm{\times}0.8\;mm$ area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1223-1229
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• 2004

A variable-gain low-voltage low noise amplifier MMIC operating at 5GHz frequency band is designed and implemented using the ETRI 0.5$\mu\textrm{m}$ GaAs MESFET library process. This low noise amplifier is designed to have the variable gain for adaptive antenna array combined in HIPERLAN/2. The feedback circuit of a resistor and channel resistance controlled by the gate voltage of enhancement MESFET is proposed for the variable-gain low noise amplifier consisted of cascaded two stages. The fabricated variable gain amplifier exhibits 5.5GHz center frequency, 14.7dB small signal gain, 10.6dB input return loss, 10.7dB output return loss, 14.4dB variable gain, and 2.98dB noise figure at V$\_$DD/=1.5V, V$\_$GGl/=0.4V, and V$\_$GG2/=0.5V. This low noise amplifier also shows-19.7dBm input PldB, -10dBm IIP3, 52.6dB SFDR, and 9.5mW power consumption.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.11-14
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• 2007

CMOS technology 기반의 고주파 직접회로에서는 충분한 이득과 안정성을 얻기 위하여 inductor, capacitor와 같은 수동 소자를 적절히 사용하여 설계하여야 한다. 이와 같은 수동 소자는 CMOS 집적회로에서 넓은 면적을 차지하는 단점이 있다. 고주파 증폭기의 부하를 능동 소자로 대체하게 되면 작은 크기로 회로의 제작이 가능하게 되나, 능동 소자는 수동 소자에 비하여 선형 특성이 좋지 않기 때문에 실제로 고주파 증폭기 설계에 사용하지 않는다. 본 논문에서는 이와 같은 능동 소자의 비선형성을 억제하면서, 동시에 회로의 크기를 줄일 수 있는 기능성 능동 부하를 적용한 고주파 증폭기를 설계하였다. 기능성 능동 부하는 2개의 MOSFET은 대칭으로 연결된 구조를 가지며, 하나의 MOSFET은 일반적인 load로 동작하며, 다른 MOSFET은 gate에 가변 전압을 인가함으로써, 증폭기의 전달함수를 변화시킬 수 있다. 이와 같은 특성을 이용하여 고주파 증폭기의 선형성을 보상할 수가 있다.