• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.1
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• pp.35-43
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• 2022

In this paper, a study was conducted to produce 20W by combining a 10W MMIC and raising the unit power amplifier to 100W SSPA by combining the 8-way spatial coupler. SSPA requires low-loss, high-efficiency coupling techniques to meet high output with the output of a single element relatively low compared to TWTA. Designed and produced in this paper, the SSPA was manufactured as a 100W SSPA by mounting eight 20W high-power amplification modules in an 8-way spatial coupler with a reflection loss of 20dB or more and an excellent coupling efficiency of 94% or more. When -10dBm was applied, it was 112.2~169.8W at 20kHz 20%, 125.9~173.8W at 400kHz 40%, 117.5~162.2W at 800kHz 40%, showing performance of over 60dB and over 100W in all three PRF conditions.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.131-138
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• 2023

In this paper, a free space optical communication device that can be used in a mobile base station of several km or less was fabricated and its characteristics were investigated. To overcome the loss due to atmospheric transmission, an optical fiber amplifier (EDFA) with an output of 23 dBm or more was used. In order to increase the focusing speed and miniaturization of the laser beam, an optical lens was manufactured, and a transmission lens was designed to have beam divergence within the range of 1.5 to 1.8 [mrad]. A PT module that controls PAN/TILT was fabricated in order to reduce pointing errors and effective automatic alignment between transceiver devices. In this study, Reed-Solomon (RS) code was used to maintain the transmission quality above a certain level. It was manufactured to be able to communicate at a wireless distance of 300m in a weather situation with visibility of 300m. For performance measurement, it was measured using BERT and eye pattern analyzer, and it was confirmed that BER can be maintained at 2.5Gbps.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.109-114
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• 2023

In this paper, a 2-channel Image-Reject receiver using a 65-nm CMOS process is presented for Ka-band compact radars. The designed receiver consists of Low-Noise Amplifier (LNA), IQ mixer, and Analog Baseband (ABB). ABB includes a complex filter in order to suppress unwanted images, and the variable gain amplifiers (VGAs) in RF block and ABB have gain tuning range from 4.5-56 dB for wide dynamic range. The gain of the receiver is controlled by on-chip SPI controllers. The receiver has noise figure of <15 dB, OP1dB of >4 dBm, image rejection ratio of >30 dB, and channel isolation of >45 dB at the voltage gain of 36 dB, in the Ka-band target frequency. The receiver consumes 420 mA at 1.2 V supply with die area of 4000×1600 ㎛.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.1-5
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• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.

• Journal of IKEEE
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• v.22 no.2
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• pp.408-412
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• 2018

In this paper, a 26GHz variable gain amplifier fabricated using a 40nm CMOS process is studied. In the case of an automobile radar using 79 GHz, it is advantageous in designing and driving to drive down to a low frequency band or to use a low frequency band before up conversion rather than designing and matching the entire circuit to 79 GHz in terms of frequency characteristics. In the case of a Phased Array System that uses time delay through TTD (True Time Delay) in practice, down conversion to a lower frequency is advantageous in realizing a real time delay and reducing errors. For a VGA (Variable Gain Amplifier) operating in the 26GHz frequency band that is 1/3 of the frequency of 79GHz, VDD : 1V, Bias 0.95V, S11 is designed to be <-9.8dB (Mea. High gain mode) and S22 < (Mea. high gain mode), Gain: 2.69dB (Mea. high gain mode), and P1dB: -15 dBm (Mea. high gain mode). In low gain mode, S11 is <-3.3dB (Mea. Low gain mode), S22 <-8.6dB (Mea. low gain mode), Gain: 0dB (Mea. low gain mode), P1dB: -21dBm (Mea. Low gain mode).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.6-13
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• 2009

For X-band phased array systems, a power amplifier, a 6-bit phase shifter, a 6-bit digital attenuator, and a SPDT transmit/receive (T/R) switch are fabricated and measured. All circuits are demonstrated by using CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascade structures. It provides 1-dB gain-compressed output power ($P_{1dB}$) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8-11 GHz frequencies. The 6-bit phase shifter utilizes embedded switched filter structure which consists of nMOS transistors as a switch and meandered microstrip lines for desired inductances. It has $360^{\circ}$ phase-control range and $5.6^{\circ}$ phase resolution. At 8-11 GHz frequencies, it has RMS phase and amplitude errors are below $5^{\circ}$ and 0.8 dB, and insertion loss of $-15.7\;{\pm}\;1,1\;dB$. The 6-bit digital attenuator is comprised of embedded switched Pi-and T-type attenuators resistive networks and nMOS switches and employes compensation circuits for low insertion phase variation. It has max. attenuation of 31.5 dB and 0.5 dB amplitude resolution. Its RMS amplitude and phase errors are below 0.4 dB and $2^{\circ}$ at 8-11 GHz frequencies, and insertion loss is $-10.5\;{\pm}\;0.8\;dB$. The SPDT T/R switch has series and shunt transistor pairs on transmit and receive path, and only one inductance to reduce chip area. It shows insertion loss of -1.5 dB, return loss below -15 dB, and isolation about -30 dB. The fabricated chip areas are $1.28\;mm^2$, $1.9mm^2$, $0.34\;mm^2$, $0.02mm^2$, respectively.

• The Korean Journal of Nuclear Medicine
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• v.33 no.1
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• pp.100-109
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• 1999

Purpose: Preamplifier and amplifier are very important parts for developing a portable counting or imaging gamma probe. They can be used for analyzing pulses containing energy and position information for the emitted radiations. The commercial Nuclear Instrument Modules (NIMs) can be used for processing these pulses. However, it may be improper to use NIMs in developing a portable gamma probe, because of its size and high price. The purpose of this study was to develop both preamplifier and amplifier and measure their performance characteristics. Materials and Methods: The preamplifier and amplifier were designed as a charge sensitive device and a capacitor resistor-resistor capacitor (CR-RC) electronic circuit, respectively, and they were mounted on a print circuit board (PCB). We acquired and analyzed energy spectra for Tc-99m and Cs-137 using both PCB and NIMs. Multichannel analyzer (Accuspec/A, Canberra Industries Inc., Meriden Connecticut, U.S.A) and scintillation detectors (EP-047(Bicron Saint-Gobain/Norton Industrial EP-047 (Ceramics Co., Ohio, U.S.A) with $2"{\times}2"$ NaI(T1) crystal and R1535 (Hamamatsu Photonics K.K., Electron Tube Center, Shizuoka-ken, Japan) with $1"{\times}1"$ NaI(T1) crystal were used for acquiring the energy spectra. Results: Using PCB, energy resolutions of EP-047 detectors for Tc-99m and Cs-137 were 12.92% and 5.01%, respectively, whereas R1535 showed 13.75% and 5.19% of energy resolution. Using the NIM devices, energy resolutions of EP-047 detector for Tc-99m and Cs-137 were measured as 14.6% and 7.58%, respectively. However, reliable energy spectrum of R1535 detector could not be acquired, since its photomultiplier tube (PMT) requires a specific type of preamplifier. Conclusion: We developed a special preamplifier and amplifier suitable for a small sized gamma probe that showed good energy resolutions independent of PMT types. The results indicate that the PCB can be used in developing both counting and imaging gamma probe.