• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.948-953
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• 2017

When using a high-power amplifier(HPA) for high-speed communication, the nonlinear characteristics of the HPA deteriorate power efficiency, bit error rate(BER) performance, and spectral efficiency. Because it is inevitable to use the HPA to obtain sufficient transmission power for high-speed communication, it is necessary to compensate for nonlinearity of the HPA by using a predistorter. In this study, a predistorter was used to compensate for the nonlinearity of the HPA, and the nonlinear distortion was compensated using the predistorter. Simulation results show that the compensation of the nonlinearity of the HPA using the predistorter achieves a BER performance similar to that of an ideal linear amplifier, and that the spectral mask is also satisfied.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.23-28
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• 2016

In this paper, a Multi-Band Ku-band down converter was designed for reception of multi-band digital satellite broadcasting. The Multi-band low-nose down converter was designed to form four local oscillator frequencies (9.75, 10, 10.75 and 11.3GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select an one band of intermediate frequency (IF) channels by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64dB, and the noise figure of low-noise amplifier was 0.7dB, the P1dB of output signal 15dBm, and the phase noise -73dBc@100Hz at the band 1 carrier frequency of 9.75GHz. The low noise block downconverter (LNB) for receiving four-band digital satellite broadcasting designed in this paper can be used for satellite broadcasting of vessels navigating international waters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6A
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• pp.862-869
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• 2000

In a switch routing system, buffers are indispensible to prevent signal collision during routing process. For a photonic switching system, optical buffers are also indispensible if the system requires an active routing rather than a simple optical cross-connect(OXC). To cope with WDM technologies in optical comminication systems in these days, photonic switching system also has to deal with WDM signals. Therefore, optical buffers needed in a switching system has to be routed to the same output. For the receiver to recognize these signals separately, parallel WDM signals during rearrangement process. In this paper, we propose a novel all optical WDM output buffer whose structure, hardware, SNR and BER characteristics are improved a lot comparing with those of previously reported ones. From the analysis of the proposed buffer, the new buffer can hold 255 WDM cells keeping BER of 10-9 as long as a contrast ratio(gain on-off ratio) of optical gate(semiconductor optical amplifier) nside the buffer is 30dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.967-973
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• 2003

This paper presents a new predistortion method which injects the 2nd low-frequency intermodulation signal of RF signals into the input bias line of the amplifier. New 2nd intermodulation signal extraction circuit is also proposed. We have shown that this method can suppress the 3rd IM apparently and sometimes do the 5th IM, through mathematical analysis, then confirmed it with simulation and verified it on the desk test. When the input signal CDMA IS-95 lFA is applied, measured ACPR improvements are 25 dBc, 22.5 dBc, and 6 dBc at 0.885 MHz, l.25 MHz and 2.25 MHz offset respectively. Also, when applying the CDMA IS-95 3FA, the measured ACPR improvement is 20 dBc at 0.885 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.282-288
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• 2014

In this paper, we have analyzed and designed a digital RF receiver based on the optimization of the dynamic range parameter to secure the wideband characteristics and linearity of digital radar receivers. To improve the wideband characteristics and dynamic range, a low noise amplifier is matching design with a noise source to minimize the noise figure in 1 GHz bandwidth and we improved the linearity of RF-receiver by securing the conversion gain characteristics of receiver through the design of active mixer. RF receiver is designed to give gain 63 dB, noise figure 1.2 dB and dynamic range of RF receiver has 75.8 dB in a wide band of 8.8~9.8 GHz. It is shown to be applicable to X-band digital radar receiver.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.5
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• pp.152-161
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• 2017

The CBTC(Communication based Train Control) system employed on 2.4GHz ISM band adopt the IEEE802.11.x standard. Therefor communication time delay, distortion and data losses will be produced. To overcome these problems, CPSK(Continuous Phase shift keying) modulated DS/SS(Direct Sequence Spread Spectrum) transmitter with 908MHz carrier frequency is proposed. Through the eye diagram and scatter diagram the performance is analysed. And the phase noise characteristic of the local oscillator is measured about 60dBc/Hz, this means that the phase noise performance is very good compared to the signal. Reference frequency suppression of the 2nd local oscillator is 50dB below compared to the signal. Through the polarities of the complementary signal equally probable, the line spectrum of the output spectrum is eliminated. The nonlinear effects which introduce the spectral spreading or spectral regeneration is reduced remarkably.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.201-206
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• 2015

A new electronically stopband tunable filter is proposed with three-input single-output using Operational Transconductance Amplifier (OTA) in this paper. The proposed filter provides band pass, low pass and high pass multifunctional responses. Centre frequency ($f_c$) and quality factor (Q) of the realized filters could independently tuned without disturbing each other. Various network sensitivity and non-ideal characteristic analysis are done to check the sensitivity and parasitic effect of different circuit parameters. The CMOS realization of filter is done with 1.8V-0.18um process parameters and HSPICE simulation results are presented to assert the presented theory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.