• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.7
• /
• pp.29-35
• /
• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• Journal of Advanced Navigation Technology
• /
• v.13 no.6
• /
• pp.838-845
• /
• 2009

In order to obtain magneto-dielectrics with various permmittivity and permeability which could be used as the antenna substrate, various magneto-dielectrics compounded of dielectric materials(such as silicon and epoxy resin) and magnetic materials(such as carbonyl iron, barium and strontium powder) were fabricated. The relative permittivity and permeability of those were measured by use of HP 4291B impedance analyzer. Based upon the measured results, inverted-F meander monopole antennas(IFA) which were printed on the magneto-dielectric substrates fabricated as film type were designed and fabricated to investigate into variations of antenna characteristics such as the resonant frequency and impedance bandwidth in comparison with use of dielectric substrate. Some simulated and measured results for the designed IFA were presented. Characteristics of magneto-dielectrics which are different according as the choice of magnetic material or the composition ratio between magnetic material and dielectric material is different have been discussed.

• The Journal of Korean Association of Computer Education
• /
• v.10 no.6
• /
• pp.69-77
• /
• 2007

In this paper we implement main functions of electronic measuring devices, which are essential to design electric/electronic virtual laboratories on the Web. The implemented virtual electronic measuring devices such as virtual analog multimeter(VAM), virtual function generator(VFG), virtual oscilloscope(VOSC) enable the learners to perform the virtual experiments on the Web by simple mouse clicks. In order to show their validity virtual experiments for understanding how to use them are designed. The virtual experiments for measuring resistance(OHM), AC/DC Voltage(ACV/DCV) and DC Current(DCA) by the VAM are illustrated. In addition, the learners can change the frequency of the signal generated from the VFG and measure by the VOSC several types of the signals generated from the VFG such as triangular, pulse, sinusoidal waveforms. The VOSC can measure voltage and current through two channels of it and provide the learners with additional functions such as zooming, trigger, cursor, summing of waveforms. Since the virtual electronic measuring devices have been implemented as forms of Java classes, various types of applications are available according to the structures of virtual laboratories.

• Journal of Korean Society of Coastal and Ocean Engineers
• /
• v.8 no.1
• /
• pp.37-43
• /
• 1996

Breaking waves were generated in a 2-D flume. A piston-type wavemaker was operated in accordance with signals which consist of elementary harmonics with appropriate phase differences. These phase differences were estimated by using a linear wave theory so that wave crests were to be concentrated at the same position. The stroke of wavemaker was controlled to create plunging-type breaking waves. The signal with small amplitude could not generate breaking waves. In the case of moderate amplitudes, various breaking waves could be obtained. Most of breaking waves were spilling type. Only when the wavemaker was operated with appropriate amplitude, plunging-type breaking waves were generated. The parameters of breaking waves are the wave steepness and the frequency bandwidth. If the central frequency was low, breaking waves were not generated. Based on experimental data, we found that the wave height of breaking inception was H = 0.0113 gT$^2$. We also made computations by using a mixed Euler-Lagrangian scheme under the assumption of potential flow. The numerical results show good agreements with tank measurements.

• Journal of IKEEE
• /
• v.23 no.1
• /
• pp.58-67
• /
• 2019

A design of an elliptic curve cryptography (ECC) processor that supports both pseudo-random curves and Koblitz curves over $GF(2^m)$ defined by the NIST standard is described in this paper. A finite field arithmetic circuit based on a word-based Montgomery multiplier was designed to support five key lengths using a datapath of fixed size, as well as to achieve a lightweight hardware implementation. In addition, Lopez-Dahab's coordinate system was adopted to remove the finite field division operation. The ECC processor was implemented in the FPGA verification platform and the hardware operation was verified by Elliptic Curve Diffie-Hellman (ECDH) key exchange protocol operation. The ECC processor that was synthesized with a 180-nm CMOS cell library occupied 10,674 gate equivalents (GEs) and a dual-port RAM of 9 kbits, and the maximum clock frequency was estimated at 154 MHz. The scalar multiplication operation over the 223-bit pseudo-random elliptic curve takes 1,112,221 clock cycles and has a throughput of 32.3 kbps.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.174-179
• /
• 2021

An Edwards curve cryptography (EdCC) core supporting point scalar multiplication (PSM) on Edwards curves of Edwards25519 and Edwards448 was designed. For area-efficient implementation, finite field multiplier based on word-based Montgomery multiplication algorithm was designed, and the extended twisted Edwards coordinates system was adopted to implement point operations without division operation. As a result of synthesizing the EdCC core with 100 MHz clock, it was implemented with 24,073 equivalent gates and 11 kbits RAM, and the maximum operating frequency was estimated to be 285 MHz. The evaluation results show that the EdCC core can compute 299 and 66 PSMs per second on Edwards25519 and Edwards448 curves, respectively. Compared to the ECC core with similar structure, the number of clock cycles required for 256-bit PSM was reduced by about 60%, resulting in 7.3 times improvement in computational performance.

• Journal of Broadcast Engineering
• /
• v.25 no.6
• /
• pp.845-853
• /
• 2020

In this paper, we propose a method for classifying environmental sound for selective noise cancellation in industrial sites. Noise in industrial sites causes hearing loss in workers, and researches on noise cancellation have been widely conducted. However, the conventional methods have a problem of blocking all sounds and cannot provide the optimal operation per noise type because of common cancellation method for all types of noise. In order to perform selective noise cancellation, therefore, we propose a method for environmental sound classification based on deep learning. The proposed method uses new sets of acoustic features consisting of temporal and statistical properties of Mel-spectrogram, which can overcome the limitation of Mel-spectrogram features, and uses convolutional neural network as a classifier. We apply the proposed method to five-class sound classification with three noise classes and two non-noise classes. We confirm that the proposed method provides improved classification accuracy by 6.6% point, compared with that using conventional Mel-spectrogram features.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.4A
• /
• pp.336-344
• /
• 2005

Discrete Wavelet Transform(DWT) is the oncoming generation of compression technique that has been selected for MPEG4 and JEPG2000, because it has no blocking effects and efficiently determines frequency property of temporary time. In this paper, we propose an efficient bit-serial architecture for the low-power and low-complexity DWT filter, employing two-channel QMF(Qudracture Mirror Filter) PR(Perfect Reconstruction) lattice filter. The filter consists of four lattices(filter length=8) and we determine the quantization bit for the coefficients by the fixed-length PSNR(peak-signal-to-noise ratio) analysis and propose the architecture of the bit-serial multiplier with the fixed coefficient. The CSD encoding for the coefficients is adopted to minimize the number of non-zero bits, thus reduces the hardware complexity. The proposed folded 1D DWT architecture processes the other resolution levels during idle periods by decimations and its efficient scheduling is proposed. The proposed architecture requires only flip-flops and full-adders. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a Hynix 0.35$\mu$m STD cell library. The maximum operating frequency is 200MHz and the throughput is 175Mbps with 16 clock latencies.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.2 no.4
• /
• pp.545-551
• /
• 1998

The Radio communication by existing SSB, VHF, etc. in a coast station and a base station for military affairs is still used to a very important the device of information delivery or transmitting and receiving by the remote controller to using to the exclusive cable for a equipment established at a long distance. When a number of consumer to connected and operated by a number of transceiver is essential for a circuit controller of ICS, in KOREA, is devoted by import to considerable quantity because of to be delayed development of this field. This Paper has been realized to optimal algorithm and designing of a circuit connection controller by multi-processor to pre-stage for the development of ICS. The H/W is composed able to remote control to circuit connector with the several slave processor and a processor for master, and this has taken possible through without any obstacle to communication circuits of a control signal by FSK system. The S/W make possible monitoring for communication condition of other circuits by means of a serial communication system by the multi-processing. This paper has been studied for connecting to a circuits wished to rapidly and precisely by the full application to a interrupt technique. A technique to control by remote to a number of transceiver is a way increasing to application for a frequency resource of the limited MF/SF, VHF and the existing radio communication technique. According to, this paper will achieve to be the reduction of energy & equipment and multiplicity of information delivery in the general communication and disposal to rapid and exact for the important communication as distress, urgency and safety on the sea.

• Journal of IKEEE
• /
• v.24 no.3
• /
• pp.901-908
• /
• 2020

This paper describes a method for scalable hardware implementation of modular inversion. The proposed scalable architecture has a one-dimensional array of processing elements (PEs) that perform arithmetic operations in 32-bit word, and its performance and hardware size can be adjusted depending on the number of PEs used. The hardware operation of the scalable processor for modular inversion was verified by implementing it on Spartan-6 FPGA device. As a result of logic synthesis with a 180-nm CMOS standard cells, the operating frequency was estimated to be in the range of 167 to 131 MHz and the gate counts were in the range of 60,000 to 91,000 gate equivalents when the number of PEs was in the range of 1 to 10. When calculating 256-bit modular inverse, the average performance was 18.7 to 118.2 Mbps, depending on the number of PEs in the range of 1 to 10. Since our scalable architecture for computing modular inversion in GF(p) has the trade-off relationship between performance and hardware complexity depending on the number of PEs used, it can be used to efficiently implement modular inversion processor optimized for performance and hardware complexity required by applications.