• Journal of Advanced Navigation Technology
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• v.10 no.4
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• pp.348-355
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• 2006

In this paper, frequency multipliers used S-band transponder of the KOMPSAT 3 are designed and fabricated. In the transponder, 108 times multiplier which generate 1st LO signal(2008.8MHz) is comprised of the X9 frequency multiplier, 1st X2 multiplier, 2nd X2 multiplier and the last stage of the X3 frequency multiplier. As results, output power of 8.17 dBm at 2008.8MHz, the harmonic suppression of -56.67dBc, the bandwidth of 14MHz were measured.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1108-1111
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• 2015

In this paper, a ${\times}49$ frequency multiplier based on a ring oscillator and a multi-push multiplier is presented. The proposed ${\times}49$ frequency multiplier consists of two ${\times}7$ frequency multipliers and these multiplier is connected by injection-locking technique. Each ${\times}7$ frequency multiplier consists of a ring oscillator with 14-phase output signal and 7-push frequency multiplier requiring 14-phase input. The proposed ${\times}49$ frequency multiplier provides 2.78~2.83 GHz output signal with 56.7~57.7 MHz input signal. This operation frequency is defined that the output power difference between the carrier and the spur is above 10 dB. The proposed chip consumes 13.93 mW.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.846-853
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• 2009

This paper presents the design of a high efficiency frequency multiplier with load-pull simulation and analyses the nonlinear distortion of the frequency multiplier. The frequency multiplier shows serious distortion of multiplying signal bandwidth because of nonlinearity when modulated signal is applied, so a digital predistortion with look up table (LUT) is applied to compensate for the distortion of the frequency multiplier. The frequency multiplier is designed to produce 5.8GHz output by doubling the input frequency to be operating at IEEE 802.11a standard wireless LAN. The output spectrum shows 12dB ACPR improvement both at +11MHz, +20MHz offset from center frequency after linearization.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.11
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• pp.1271-1278
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• 2007

A novel frequency multiplier using composite right/left-handed transmission line is proposed. The left-handed transmission line in the proposed frequency multiplier suppresses the fundamental component($f_0$), while the composite right/left-handed ${\lambda}/4$ open stub diminishes unwanted harmonics. Due to the combination of the left-handed transmission line and composite right/left-handed ${\lambda}/4$ open stub, the only desirable multiplied frequency component such as 3 $f_0$ and 4 $f_0$ are obtained at the output port excellently. For the example of the proposed design, frequency multipliers are designed at 1 GHz of $f_0$ and measured. The measured output power of 3 $f_0$ and 4 $f_0$ is -5.67 dBm and -6.43 dBm, respectively, when the fundamental input power was 0 dBm.

• Journal of the Korean Institute of Telematics and Electronics
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• v.4 no.1
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• pp.22-26
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• 1967

The efficiency of frequency multiplier using nonlinear elements varies with the characteristics of the elements and also varies with the order of multiplication. And, if the elements is resistive, the efficiency varies with reverse-to-forward resistance value. Microwave energy which was frequency doubled by a nonlinear resistive element was obtained, and the theoretical efficiency of nonlinear reactive and resistive multiplier were compared with the efficiency taken by experiments. It was found that efficiency of frequency multiplier using the nonlinear resistive elements was increased, without depending on frequency, with the reverse-to-forward resistance value.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1137-1140
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• 2011

In this paper, the optimal condition for efficient active frequency multipliers is analyzed. This analysis is based on the effects from transistor nonlinear coefficients, harmonic impedances, and output parasitic components. From the analysis, normalized harmonic power is estimated with the clipping condition of a commercial transistor, and the condition for high conversion efficiency is suggested. From the analysis, a class-F frequency tripler was implemented for the output at 2.475 GHz, showing the maximum efficiency of 22.9 % and the maximum conversion gain of 9.5 dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.122-128
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• 2005

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are designed and implemented. As the fundamental signal of the oscillator for frequency doubling is extracted between the dielectric resonator (DR) filter and the gate device of the active device, the undesired harmonics at the output of the oscillator is remarkably suppressed. The fundamental signal of the oscillator for frequency doubling directly feeds to the frequency doubler without an additional band pass filter for harmonic suppression. The second harmonic suppression of -47.7 dBc at the oscillator output is achieved, while the fundamental suppression of -37.5 dBc at the doubler output is obtained. The phase noise characteristics are -80.3 dBc/Hz and -93.5 dBc/Hz at the offset frequency of 10 KHz and 100 KHz from the carrier, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.725-731
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• 2006

A novel design of frequency multiplier using a feedforward technique and a defected ground structure(DGS) is proposed. The feedforward loop in the proposed frequency multiplier suppresses the fundamental component $(f_0)$, the dumb-bell or spiral shaped DGS diminish unwanted harmonics such as second, third and fourth. Due to the combination of the feedforward structure and the DGS, only the multiplied frequency component$(2f_0,\;3f_0,\;4f_0)$ appears at the output port and the other unwanted components are suppressed excellently. The frequency multiplier is designed at 1 GHz $(f_0)$, by the proposed technique and measured. The measured output power of $2f_0,\;3f_0$ and $4f_0$ is -2.59 dBm, -5.36dBm and -4.57dBm, respectively, when the input power is 0dBm.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.391-396
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• 2010

This paper presents some important research result comparisons for multi function RF modules which use amplifier or frequency multiplier. By using multiplier, multi function module can be realized amply in comparison to multi band module which has separate block for each frequency band. Some com paring analysis among the switching method between separate amplifier and multiplier, the structure using frequency selective reflector, and the module using the defected ground structure. The multi function module which operates as amplifier or multiplier with input frequency is developed and input frequency suppression and output harmonics suppression can be improve d by using defected ground structure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.10
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• pp.971-978
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• 2013

This work presents a W band frequency synthesizer which is composed of 26 GHz VCO, Phase Locked Loop and frequency tripler using 65 nm RF CMOS process. Frequency tuning range of 26 GHz VCO covers the band from 22.8~26.8 GHz and final output frequency of the tripler is from 74 to 75.6 GHz. The fabricated frequency synthesizer consumes 75.6 mW and its phase noise is -75 dBc/Hz at 1 MHz offset, -101 dBc/Hz 10 MHz offset respectively.