• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.6
• /
• pp.51-57
• /
• 2017

In this paper, we designed a frequency synthesizer using DDS (Direct Digital Synthesizer) for Ka-band compact Radar. DDS is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and Ka band frequency up-converter are integrated in one module. Proposed frequency synthesizer provides LFM(Linear Frequency Modulation) waveform and Phase modulated FMCW (Frequency Modulation Continuous Wave) waveform. It is observed that fabricated synthesizer performs $0.191{\mu}sec$ frequency switching time and -89.16 dBc/Hz phase noise at offset 1 kHz.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.49 no.1
• /
• pp.85-91
• /
• 2012

In this paper, we implemented a Ka-band frequency synthesizer for millimeter wave seeker. we designed for high frequency resolution and frequency hopping response time in the digital synthesis method which uses DDS(Direct Digital Synthesizer). but frequency bandwidth was limited low frequency because DDS output frequency was limited 1/2 by system clock. thus, frequency synthesizer was converted to Ka-band using the frequency multiplier ${\times}4$ and local oscillator. proposed frequency synthesizer was bandwidth 500MHz, frequency switching time was $0.7{\mu}s$, spurious level was suppressed below -52dBc. phase noise was -99dBc/Hz at offset 100kHz and flatness was ${\pm}1dB$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.64-72
• /
• 2010

This paper presents a wide range VCO with fine coarse tuning step using a sigma-delta modulation technique for UWB frequency synthesizer. The proposed coarse tuning scheme provides the low effective frequency resolution without any degradation of phase noise performance. With three steps coarse tuning, the VCO has wide tuning range and fine tuning step simultaneously. The frequency synthesizer with VCO was implemented with 0.13 ${\mu}m$ CMOS technology. The tuning range of the VCO is 5.8 GHz~6.8 GHz with the effective frequency resolution of 3.9 kHz. It achieves the measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range 16.8 % with 5.9 mW power. The figure-of-merit with the tuning range is -181.5 dBc/Hz.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.1
• /
• pp.69-78
• /
• 2007

A Frequency synthesizer for T-DMB and mobile-DTV applications was designed using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors were chosen for VCO core to reduce phase noise. The VCO range is 920MHz-2100MHz using switchable inductors, capacitors and varactors. Varactor biases that improve varactor acitance characteristics were minimized as two, and $K_{VCO}$(VCO gain) value was aintained by switchable varactor. Additionally, VCO was designed that VCO gain and the interval of VCO gain were maintained using VCO gain compensation logic. VCO, PFD, CP and LF were verified by Cadence Spectre, and divider was simulated using Matlab Simulink, ModelSim and HSPICE. VCO consumes 10mW power, and is 56.3% tuning range. VCO phase noise is -127dBc/Hz at 1MHz offset for 1.58GHz output frequency. Total power consumption of the frequency synthesizer is 18mW, and lock time is about $140{\mu}s$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.8
• /
• pp.1099-1106
• /
• 2018

In this paper, we developed and then analyzed the specifications of the frequency synthesizer which was applied to long range MFR (Multi-function Radar). These specifications were able to guarantee the functions and performance of MFR. MFR was the radar system that used phase array for electronically scanning. This frequency synthesizer made various frequency signals including to STALO (Stable Local Oscillator) for MFR. By analyzing the MFR requirements, we choose the optimal frequency synthesis method and then we got the best performance and functionality including to physical size for this system. We designed and fabricated DDS (Direct Digital Synthesizer)-driven Offset-PLL (Phase Locked Loop) synthesizer to meet the requirements which were low phase noise, fast switching time and low spurious. This synthesizer had less than -131dBc/Hz@100kHz phase noise and less than $4.1{\mu}s$ switching time, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.6
• /
• pp.551-561
• /
• 2009

FH system is very robust to the jamming interference. OFDM system is very good for the high speed communication system. But, it has high PAPR. SC-FDMA system based on OFT-spread OFDM was proposed to reduce high PAPR. Therefore, in this paper, we like to introduce the FH system into SC-FDMA system, which can be best solution to the jamming hostile environment and for the high power efficiency. Also, OFDM is very sensitive to ICI. Especially, ICI generated by frequency offset and phase noise breaks the orthogonality among sub-carriers, which seriously degrades the system performance. We analyze the performance of the FH SC-FDMA system in the PBJ and MTJ channel. In this paper, the ICI effects caused by phase noise, frequency offset and Doppler effects are analyzed and we like to propose the PNFS algorithm in the equalizer to compensate the ICI influences. Through the computer simulations, we can confirm the performance improvement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.11
• /
• pp.1075-1081
• /
• 2004

In this paper, a VCO of a general advance warning system for vehicle's speed limitation in the X-band used in Japan is designed using a small signal scattering coefficient of PHEMT. A varactor diode that wide tuning range and series resistance 0 H is used for designing the VCO and -85 dBc/Hz of phase noise at 10 kHz of offset frequency is obtained by adjusting the reflection coefficient between the micro-strip line and the varactor device which determines transistor's operation voltage and resonant frequency, In addition +4.5 dBm of basic frequency signal output level and -25.6 dEc of the second harmonic constraint are acquired. Sample that produce in this paper could confirm that more excellent special quality appears than existing products in sensitivity.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.25 no.12
• /
• pp.1236-1242
• /
• 2014

In this work, a D-band VCO(Voltage Controlled Oscillator) has been developed in a 65-nm CMOS technology. The circuit was designed based on push-push mechanism. The output oscillation frequency of the fabricated VCO varied from 152.7 GHz to 165.8 GHz, and the measured output power was from -17.3 dBm to -8.7 dBm. A phase noise of -90.9 dBc/Hz is achieved at 10 MHz offset. The chip size of the circuit is $470{\mu}m{\times}360{\mu}m$ including the probing pads.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.10
• /
• pp.2129-2135
• /
• 2011

The WLAN and WPAN systems employed on 2.4GHz ISM band wireless networks provide complementary services within the same environments. Coexistence between the networks will be impaired, if the mutual packets are uncertainty associated the timing or gaussian distance. This paper analyzes the impact of the mutual interference on the services performance and in order to minimize the effect of WPAN system signals on the WLAN system, proposed a method of suppressing the interference on the WLAN system. The analysis is illustrated by examining the symbol error rate versus signal to noise interference ratio in terms of the carrier frequency offset.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1A
• /
• pp.18-30
• /
• 2004

In this paper, the calibration problem of an asynchronous CDMA-based antenna array is studied. A new iterative calibration algorithm for antenna array in the presence of frequency offset error is presented. The algorithm is applicable to a non-linear array and does not require a prior knowledge of the (direction of arrivals) DOAs of the signals of any user, and it only requires the code sequence of a reference user. The algorithm is based on the two step procedures, one for estimating both channel and frequency offset and the other for estimating the unknown array gain and phase. Consequently, estimates of the DOAs, the multi-path impulse response of the reference signal sources, and the carrier frequency offset as well as the calibration of antenna array are provided. The performance of the proposed algorithm is investigated by means of computer simulations and is verified by using field data measured through a custom-built W-CDMA test-bed.