• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.19-19
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• 2017

자율주행 트랙터를 위한 트랙터 조향제어는 일반적으로 전자모터를 이용한 EPS(Electric Power Steering) 시스템을 스티어링 휠에 연결하여 회전변위를 변경하고 그 결과 오비트롤(Orbitrol) 밸브의 토출유량을 바꾸고 호스로 연결된 조향실린더의 변위를 조절하여 최종적으로 전방 타이어의 방향각을 변경하면서 이루어진다. 이러한 조향방식은 시스템 구조상 조향실린더와 오비트롤 밸브가 상대적으로 멀리 떨어져 있으며, 밸브 특성상 약 ${\pm}5^{\circ}$의 오버랩이 포함되어 있다. 또한, EPS의 전자모터는 관성력, 마찰, 백래시 등의 영향을 가진다. 이와 같은 복합적인 영향은 조향 응답을 느리게 만들어 상대적으로 빠른 속도에서 주행에서 추종성능이 떨어지는 문제가 발생한다. 본 연구에서는 자율주행 트랙터의 조향성능 개선 연구의 일환으로 조향 HILS 시뮬레이터를 설계제작하여 조향 성능의 요인을 실험적으로 구명하고자 하였으며 이를 바탕으로 조향 시스템의 설계개선 방안을 수립하고자 하였다. 시뮬레이터는 동양물산 80 마력급 TX803 트랙터에 사용되는 오픈센터방식의 오비트롤 유압회로 시스템을 기어펌프가 장착된 AC모터로 구동되게 구성하였으며, 유량은 모터의 주파수를 조절 회전속도를 조절 변경하였다. 추가적으로 EPS와 오비트롤 조합의 조향성능을 비교 및 개선하기 위해 비례제어밸브(PVG 32, Danfoss)를 추가 장착하였다. 실제 트랙터 조향 시 나타나는 마찰저항을 모사하기 위해 부하 실린더를 구성하였으며, 조향 실린더의 부하의 크기는 부하 실린더를 폐회로를 구성하고 유량비례제어밸브를 이용한 유로의 개구량 조절을 통해 부하의 크기를 약 4000 N 까지 증가시킬 수 있도록 하였다. EPS와 비례제어밸브를 제어하기 위해 CANoe 8.0 소프트웨어를 이용하여 CAN통신 기반 가상 조향ECU를 구성하였으며 오비트롤의 기본 성능을 확인하기 위해 조향휠에 따른 실린더 동특성 및 계단 추종성능을 비례제어밸브와 비교하였다. 오비트롤 밸브는 약 ${\pm}5^{\circ}$이상 동작 시 실린더 압력이 상승하기 시작하였으며, 이후 약 ${\pm}10^{\circ}$이상 동작 시 조향실린더가 동작하기 시작하였다. 계단 추종성능실험에서는 비례제어밸브가 약 2배 이상의 응답개선을 나타냈다. 자율주행 경로추종 성능을 향상시키기 위해서는 순간적인 출력밀도가 높은 비례제어밸브를 통해 응답개선이 필요한 것으로 나타났다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.1
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• pp.94-101
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• 2009

This paper presents scalable modeling of spiral inductors for RFIC design based on $0.13{\mu}m$ RF CMOS process. For scalable modeling, several inductor patterns are designed and fabricated with variations of width, number of turns and inner radius. Feeding structures are optimized for accurate de-embedding of pad effects. After measuring the S parameters of the fabricated patterns, double-$\pi$ equivalent circuit parameters are extracted for each device and their geometrical dependences are modeled as scalable functions. The inductor library provides two types of models including standard and symmetric inductors. Standard and symmetric inductors have the range of $0.12{\sim}10.7nH$ and $0.08{\sim}13.6nH$ respectively. The models are valid up to 30GHz or self-resonance frequency. Through this research, a scalable inductor library with an error rate below 10% is developed for $0.13{\mu}m$ RF CMOS process.

• Journal of Sensor Science and Technology
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• v.10 no.4
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• pp.214-221
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• 2001

The use of an asymmetric Mach-Zehnder interferometric amplitude modulator to measure a relatively low frequency electric field strength is described. The sensitivity of an electric field sensor using a $Ti:LiMbO_3$ optical modulator is strongly affected by the shape of a electrode(probe antenna). To measure the low frequency electric field, a probe antenna of wide effective area is more useful than the usual dipole antenna. As a proof of this, the optical modulator was fabricated with a plate-type probe antenna and the usefulness of this antenna tested for measuring low frequency electric field strength. Measurements were performed in the range 0.1 V/cm to 60 V/cm at 60Hz through 100 kHz. Using a probe antenna of $10\;mm{\times}10\;mm$, the output voltage of $10^{-2}\;mV$ was measured with respect to the electric field strength of 0.1 V/cm at 60 Hz. By increasing the effective area of the probe antenna, better sensitivity is obtainable over the measured range.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• Journal of Korea Multimedia Society
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• v.15 no.2
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• pp.179-194
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• 2012

Digital image forgery is becoming a topic of great interest with regard to honesty in imaging. We can often see forged digital images in a variety of places, such as the internet, and magazines, and in images used in political ads, etc. These can reduce the reliability and factual basis of the information contained in image. Therefore, objectivity is needed to determine if the image is forged so as to prevent confusion in the viewing public. Most digital forgeries consist of image resizing, rotating including the following interpolations. To find evidence of interpolation in forged images, this paper proposes a new method for detecting digital image forgery using general interpolation factors analyzed through re-interpolation algorithm of the forged images in order to determine the differences in the patterns. Through the re-interpolation algorithm we could detect the forged region and filtering region used image retouching included to interpolation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.453-458
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• 2010

In this work, a 18 GHz divide-by-4 injection-locked frequency divider(ILFD) based on ring oscillator has been developed in $0.13-{\mu}m$ Si RFCMOS technology. The free-running oscillation frequency is from 4.98 to 5.22 GHz and output power is about －30 dBm, consuming 33.4 mW with a 1.5 V supply voltage. At 0 dBm input power, the locking range is 3.5 GHz(17.75~21.25 GHz) and with varactor tuning, the operating range is increased up to 5.25 GHz(16.0~21.25 GHz). The fabricated chip size is $0.76\;mm{\times}0.57\;mm$ including DC and RF pad.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.9
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• pp.613-620
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• 2016

In order to scrutinize the fluid conductivity effects on the electromagnetic flowmeter(EMF) characteristics, a small scale EMF was designed and fabricated. The measuring tube has a $3mm{\times}4mm$ rectangular cross-section, 9 mm length, and a $2mm{\times}3mm$ plate electrode and a ${\Phi}1.5mm$ point electrode. The design parameters, such as the magnetizing frequency and the number of coil turns, and the diameter were optimized. The EMF was tested with a gravimetric calibrator and showed good linearity in the range of 0 to $1.17{\times}10^{-5}m^3/s$. The fluid conductivity was varied between 3 and $11{\mu}S/cm$, and the magnitude of the flow signal was proportional to the fluid conductivity and the wetted area of the electrode. The design information and the test results provide flow measurement techniques for very low flowrate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.12
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• pp.1346-1351
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• 2014

We propose a novel approach for stereophonic acoustic echo suppression using spectro-temporal filtering based on soft decision. Unlike the conventional approaches estimating the echo pathes directly, the proposed technique can estimate stereo echo spectra without any double-talk detector. In order to improve the estimation of echo spectra, the extended power spectrum density matrix and echo overestimation control matrix are applied on this method. In addition, this echo suppression technique is based on soft decision technique using speech absence probability in STFT domain. Experimental results show that the proposed method improves compared with the conventional approaches.

• The Journal of the Acoustical Society of Korea
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• v.21 no.3
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• pp.304-309
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• 2002

We propose the computation reduction method of real root method that is mainly used in the CELP (Code Excited Linear Prediction) vocoder. The real root method is that if polynomial equations have the real roots, we are able to find those and transform them into LSP. However, this method takes much time to compute, because the root searching is processed sequentially in frequency region. In this paper, to reduce the computation time of real root, we compare the real root method with two methods. In first method, we use the mal scale of searching frequency region that is linear below 1 kHz and logarithmic above. In second method, The searching frequency region and searching interval are ordered by each coefficient's distribution. In order to compare real root method with proposed methods, we measured the following two. First, we compared the position of transformed LSP (Line Spectrum Pairs) parameters in the proposed methods with these of real root method. Second, we measured how long computation time is reduced. The experimental results of both methods that the searching time was reduced by about 47% in average without the change of LSP parameters.