• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.301-301
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• 2010

현재 전 세계는 앞으로 사용 될 대체 에너지에 많은 관심 가지고 있다. 지금 사용하고 있는 에너지 연료는 한정되어 있기 때문에 대체에너지에 대한 연구가 활발히 진행 되고 있다. 그 중 압전체를 이용한 에너지 하베스팅은 많은 주목을 받고 있다. 주변 환경에서 필요한 에너지를 끌어 쓸 수 있는 대표적인 청정에너지 시스템 중 하나이기 때문이다. 최근 전원 공급원으로써 에너지 수확 시스템은 현 사회에 사용되고 있는 배터리로 전원을 사용하는 제품들을 소용량과 저전압 분야에서의 에너지 수확의 원리를 이용하여 전기전자제품의 사용시간 연장 및 응용분야 확대를 시도하는 연구가 활발히 수행되고 있다. 압전세라믹스를 이용한 에너지 하베스팅은 진동에너지를 전기에너지로 변환하는 것으로서 압전 특성이 높아야 한다. 일반적으로 압전 세라믹스는 PbO 성분이 들어가므로 환경적 오염 뿐만 아니라 인체에도 영향이 좋지 않으므로 많은 나라에서 이러한 성분을 제한하고 점차적으로 줄어들고 있는 시점에서 PbO를 사용하지 않고 Lead-Free 세라믹를 사용한 연구가 진행되고 있다. 이 논문에서는 일반적인 소결 방법을 이용하여 (Na,K)NbO3 세라믹에 CeO2를 첨가한 압전 세라믹을 제작하였다. 제작된 압전 세라믹스로 에너지 하베스팅 소자를 제작하고, 이 소자로 수확된 에너지로 DC-DC Converter 응용 특성에 대하서 연구하였다. 압전 세라믹스의 좋은 압전 특성을 출력하기 위하여 캔틸레버의 고유 진동수가 진동원의 주파수와 일치하는 공진을 일으켜야 한다. 따라서 구동회로는 주파수원을 찾아 설계하였고, 압전 세라믹스의 진동은 가진기를 이용하여 구동실험을 하였다. 지금까지 나와있던 에너지 하베스팅 회로와 비교하여 그 특성을 분석하고, 시뮬레이션 및 실험을 통하여 검증하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.457-457
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• 2014

오존발생방법은 다양한 방식으로 구현이 가능하나 대용량 장치를 만들기 위해서는 DBD (Dielectric barrier discharge) 구조의 형태의 가지고 있다. 이러한, DBD는 반도체의 MOS (Metal On Semiconductor)의 반대 구조를 가진 SOM (Semiconductor On Metal)의 형태를 가지고 있으며 대부분이 Oxidation 산화물을 가지고 구현한다. 오존발생기는 반도체 공정, 환경 및 정화 등 다양한 분야에 사용이 되고 있는 상황으로 성능개선을 위한 연구가 필요한 상황이다. 대표적으로 사용되는 물질인 $SiO_2$를 가지고 있는 상황이며 Silicon은 에너지 Bandgap이 1.1 eV로 금속위에 증착되어 통상적으로 사용되는 문턱전압은 0.7 V에 해당이 된다. 현재 점차적으로 연구가 진행되고 있는 $Al_2O_3$는 8.8 eV의 bandgap을 가지고 있으며 유전 상수가 9로 $SiO_2$인 3.9보다 높은 유전률 특징을 가지고 있다. 따라서, 본 연구는 오존 발생장치에 사용되는 방전관을 기존의 $SiO_2$에서 $Al_2O_3$ 방식으로 대체하므로써 실제적인 유전율의 값의 차이와 오존 발생시 오존변화율 증대에 관하여 연구하였다. $SiO_2$ 방전관은 Fe 메탈위에 약 3 mm정도의 두께를 binding시켜 N4L사의 PSM1700 모델 LCR meter를 사용하여 1.3 kHz시 7.2 pF의 유전율 확인 할 수 있으며 동일한 조건의 금속 메탈위에 $Al_2O_3$를 binding 시켜 측정한 결과 1.07 kHz시 10.7 pF의 유전율을 가지게 되어 40% 이상 높은 유전율을 가지게 되는 것을 확인 할 수 있다. 오존발생을 위하여 가변 주파수형 트랜스 드라이버를 통한 공진 주파수를 생성하여 방전 증폭을 위한 Amplifier를 통하여 변환률을 높이는 방식을 적용하여 MIDAC사의 I1801모델 적외선 분광기(FT-IR)를 통한 오존발생량을 측정하여 기존의 $SiO_2$의 방전관은 시간당 54 g의 오존 발생률 가지게 된다. $Al_2O_3$는 시간당 70 g 정도의 오존 발생률 가지므로 기존의 $SiO_2$ 보다 발생률 높은 것을 확인 할 수 있다.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.1
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• pp.90-100
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• 1993

A finite element formulation of vibration control of a laminated plate with piezoelectric sensor/ actuators is presented. Classical lamination theory with the induced strain actuation and Hamilton's principle are used to formulate the equations of motion of the system. The total charge developed on the sensor layer is calculated from the direct piezoelectric equation. The equations of motion and the total charge are discretized with 4 node, 12 degrees of freedom quadrilateral plate bending elements with one electrical degree of freedom. The mass and stiffness of the piezoelectric layer are introduced by treating them as another layer in laminated plate. Piezoelectric sensor/actuators are distributed, but discrete due to the geometry of electrodes. By defining an i.d. number of electrode for each element, modelling of electrodes with variable geometry can be achieved. The static response of a piezoelectric bimorph beam to electrical loading and sensor voltage to given displacement are calculated. For a laminated plate under the negative velocity feedback control, the direct time response by the Newmark-.betha. method and damped frequencies and modal damping ratios by modal state space analysis are derived.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.67-74
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• 2013

A low-power 12-bit resistor string DAC for wireless sensor applications is presented. Two-step approach reduces complexity, minimizes power consumption and area, and increases speed. This chip is fabricated in 0.18-${\mu}m$ CMOS and the die area is $0.76mm{\times}0.56mm$. The measured power consumption is 1.8mW from the supply voltage of 1.8V. Measured SFDR(Spurious-Free Dynamic Range) is 70dB when the sampling frequency is less than 1 MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2227-2235
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• 2009

This paper describes the system configuration and measured performances of a wireless power transmission system which utilizes microwave. The technically final target of this system is to provide DC power to various mobile terminals within limited spaces such as buildings, conference rooms, and so on. The prototype system is built using in-house designed and fabricated circuits such as microwave oscillator, high power amplifier, microstrip patch antenna, low pass filter, and detector/rectifier. The fixed RF power of 29.3dBm at 2.4GHz is produced from the high power amplifier and transmitted through the transmitting antenna, while the received RF power at the receiving antenna is transformed into DC power through the detector/rectifier. The measured change of DC voltage according to the distance between transmitting and receiving antenna is described.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.63-73
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• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.262-265
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• 2012

In this paper, a Ka-band 8 W power amplifier module with WR-28 waveguide input and output ports is implemented and measured using four 2 W power amplifier modules and 4:1 waveguide power combiners with high isolation of 25 dB at 35 GHz. The 2 W power amplifier modules are fabricated using waveguide-to-microstrip transitions and show output power of 32.5~33.3 dBm and power gain of 26.9~28.7 dB at 35 GHz. Four 2 W power amplifier modules are combined through 4:1 waveguide power combiners with resistive septum and the combined power shows 39.0 dBm(8 W) under 6 V drain bias and 39.6 dBm(9.1 W) under 6.5 V drain bias at 35 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.