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Development of Fiber-end-cap Fabrication Equipment (대구경 광섬유 엔드캡 제작장비 개발)

  • Lee, Sung Hun;Hwang, Soon Hwi;Kim, Tae Kyun;Yang, Whan Seok;Yoon, Yeong Gap;Kim, Seon Ju
    • Korean Journal of Optics and Photonics
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    • v.32 no.2
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    • pp.49-54
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    • 2021
  • In this paper, we design and construct the equipment to manufacture large-diameter optical fiber end caps, which are the core parts of high-power fiber lasers, and we fabricate large-diameter optical fiber end caps using the home-made equipment. This equipment consists of a CO2 laser as a fusion-splice heat source, a precision stage assembly for transferring the position of a large-diameter optical fiber and an end cap, and a vision system used for alignment when the fusion splice is interlocked with the stage assembly. The output of the laser source is interlocked with the stage assembly to control the output, and the equipment is manufactured to align the polarization axis of the large-diameter polarization-maintaining optical fiber with the vision system. Optical fiber end caps were manufactured by laser fusion splicing of a large-diameter polarization-maintaining optical fiber with a clad diameter of 400 ㎛ and an end cap of 10×5×2 ㎣ (W×D×H) using home-made equipment. Signal-light insertion loss, polarization extinction ratio, and beam quality M2 of the fabricated large-diameter optical fiber end caps were measured to be 0.6%, 16.7 dB, and 1.21, respectively.

The Development of a Benthic Chamber (BelcI) for Benthic Boundary Layer Studies (저층 경계면 연구용 Benthic chamber(BelcI) 개발)

  • Lee, Jae-Seong;Bahk, Kyung-Soo;Khang, Buem-Joo;Kim, Young-Tae;Bae, Jae-Hyun;Kim, Seong-Soo;Park, Jung-Jun;Choi, Ok-In
    • The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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    • v.15 no.1
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    • pp.41-50
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    • 2010
  • We have developed an in-situ benthic chamber (BelcI) for use in coastal studies that can be deployed from a small boat. It is expected that BelcI will be useful in studying the benthic boundary layer because of its flexibility. BelcI is divided into three main areas: 1) frame and body chamber, 2) water sampler, and 3) stirring devices, electric controller, and data acquisition technology. To maximize in-situ use, the frame is constructed from two layers that consist of square cells. All electronic parts (motor controller, pA meter, data acquisition, etc.) are low-power consumers so that the external power supply can be safely removed from the system. The hydrodynamics of BelcI, measured by PIV (particle image velocimetry), show a typical "radial-flow impeller" pattern. Mixing time of water in the chamber is about 30 s, and shear velocity ($u^*$) near the bottom layer was calculated at $0.32\;cm\;s^{-1}$. Measurements of diffusivity boundary layer thickness showed a range of $180-230\;{\mu}m$. Sediment oxygen consumption rate, measured in-situ,was $84\;mmol\;O_2\;m^{-2}\;d_{-1}$, more than two times higher than on-board incubation results. Benthic fluxes assessed from in-situ incubation were estimated as follows: nitrate + nitrite = $0.18\;{\pm}\;0.07\;mmol\;m^{-2}\;d^{-1}$ ammonium $23\;{\pm}\;1\;mmol\;m^{-2}\;d^{-1}$ phosphate = $0.09\;{\pm}\;0.02\;mmol\;m^{-2}\;d^{-1}$ and silicate = $23\;{\pm}\;1\;mmol\;m^{-2}\;d^{-1}$.

A Study on Implementation and Performance of the Power Control High Power Amplifier for Satellite Mobile Communication System (위성통신용 전력제어 고출력증폭기의 구현 및 성능평가에 관한 연구)

  • 전중성;김동일;배정철
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.1
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    • pp.77-88
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    • 2000
  • In this paper, the 3-mode variable gain high power amplifier for a transmitter of INMARSAT-B operating at L-band(1626.5-1646.5 MHz) was developed. This SSPA can amplify 42 dBm in high power mode, 38 dBm in medium power mode and 36 dBm in low power mode for INMARSAT-B. The allowable errol sets +1 dBm as the upper limit and -2 dBm as the lower limit, respectively. To simplify the fabrication process, the whole system is designed by two parts composed of a driving amplifier and a high power amplifier. The HP's MGA-64135 and Motorola's MRF-6401 were used for driving amplifier, and the ERICSSON's PTE-10114 and PTF-10021 for the high power amplifier. The SSPA was fabricated by the RP circuits, the temperature compensation circuits and 3-mode variable gain control circuits and 20 dB parallel coupled-line directional coupler in aluminum housing. In addition, the gain control method was proposed by digital attenuator for 3-mode amplifier. Then il has been experimentally verified that the gain is controlled for single tone signal as well as two tone signals. In this case, the SSPA detects the output power by 20 dB parallel coupled-line directional coupler and phase non-splitter amplifier. The realized SSPA has 41.6 dB, 37.6 dB and 33.2 dB for small signal gain within 20 MHz bandwidth, and the VSWR of input and output port is less than 1.3:1. The minimum value of the 1 dB compression point gets more than 12 dBm for 3-mode variable gain high power amplifier. A typical two tone intermodulation point has 36.5 dBc maximum which is single carrier backed off 3 dB from 1 dB compression point. The maximum output power of 43 dBm was achieved at the 1636.5 MHz. These results reveal a high power of 20 Watt, which was the design target.

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A Fast Processor Architecture and 2-D Data Scheduling Method to Implement the Lifting Scheme 2-D Discrete Wavelet Transform (리프팅 스킴의 2차원 이산 웨이브릿 변환 하드웨어 구현을 위한 고속 프로세서 구조 및 2차원 데이터 스케줄링 방법)

  • Kim Jong Woog;Chong Jong Wha
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.19-28
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    • 2005
  • In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

A 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting applications (DMB 응용을 위한 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D 변환기)

  • Cho, Young-Jae;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.11 s.353
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    • pp.37-47
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    • 2006
  • This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

Analysis of the Effect of the Etching Process and Ion Injection Process in the Unit Process for the Development of High Voltage Power Semiconductor Devices (고전압 전력반도체 소자 개발을 위한 단위공정에서 식각공정과 이온주입공정의 영향 분석)

  • Gyu Cheol Choi;KyungBeom Kim;Bonghwan Kim;Jong Min Kim;SangMok Chang
    • Clean Technology
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    • v.29 no.4
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    • pp.255-261
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    • 2023
  • Power semiconductors are semiconductors used for power conversion, transformation, distribution, and control. Recently, the global demand for high-voltage power semiconductors is increasing across various industrial fields, and optimization research on high-voltage IGBT components is urgently needed in these industries. For high-voltage IGBT development, setting the resistance value of the wafer and optimizing key unit processes are major variables in the electrical characteristics of the finished chip. Furthermore, the securing process and optimization of the technology to support high breakdown voltage is also important. Etching is a process of transferring the pattern of the mask circuit in the photolithography process to the wafer and removing unnecessary parts at the bottom of the photoresist film. Ion implantation is a process of injecting impurities along with thermal diffusion technology into the wafer substrate during the semiconductor manufacturing process. This process helps achieve a certain conductivity. In this study, dry etching and wet etching were controlled during field ring etching, which is an important process for forming a ring structure that supports the 3.3 kV breakdown voltage of IGBT, in order to analyze four conditions and form a stable body junction depth to secure the breakdown voltage. The field ring ion implantation process was optimized based on the TEG design by dividing it into four conditions. The wet etching 1-step method was advantageous in terms of process and work efficiency, and the ring pattern ion implantation conditions showed a doping concentration of 9.0E13 and an energy of 120 keV. The p-ion implantation conditions were optimized at a doping concentration of 6.5E13 and an energy of 80 keV, and the p+ ion implantation conditions were optimized at a doping concentration of 3.0E15 and an energy of 160 keV.