• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.488-496
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• 2012

In this paper, the scheme for designing optimal beamforming matrix for interference control is proposed. The optimal beamforming matrix is found though linear combination of interference alignment conditions and renewal of linear combination coefficient. The proposed scheme has advantages that the complexity is reduced and there is no multiplying operation in matrix calculations even if proposed scheme has the form similar to that of existing least square based scheme. The simulation results show that proposed scheme has about 4bps/Hz higher gain than existing least square scheme. Also there is no additional multiplying calculation and increase of matrix size when the number of transmit and receive antennas is increased.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.327-331
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• 2008

Optimal Extension Fields (OEFs) are finite fields of a special form which are very useful for software implementation of elliptic curve cryptosystems. Bailey and Paar introduced efficient OEF arithmetic algorithms including the $p^ith$ powering operation, and an efficient algorithm to construct OEFs for cryptographic use. In this paper, we give a counterexample where their $p^ith$ powering algorithm does not work, and show that their OEF construction algorithm is faulty, i.e., it may produce some non-OEFs as output. We present improved algorithms which correct these problems, and give improved statistics for the number of OEFs.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.561-566
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• 2013

We propose an efficient exponentiation method which is resistant against some side channel attacks in $T_2(p)$, Torus-Based-Cryptosystem. It is more efficient than the general exponentiation method in $T_2(p)$ and is resistant against SPA by using that the difference of squaring and multiplication costs is negligible. Moreover, we can randomize a message in exponentiation step using the characteristic of quotient group which naturally protects against the first DPA.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.173-182
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• 1995

모듈라 멱승(modular exponentiation) 연산은 암호학에서 기본적이고 중요한 연산이다. 그러나, 이는 다정도 정수(multiple precision integer)들을 다루기 때문에 그 연산시 간이 무척 많이 걸리므로 이를 단축시킬 필요가 있다. 모듈라 멱승 연산은 모듈라 곱셈(modular multiplication)의 반복으로서, 전체 연산시간을 단축시키기 위해서는 모듈라 곱셈의 수행시간을 단축시키거나, 모듈라 곱셈의 반복횟수를 줄이는 것이 필요하다. 본 논문에서는 모듈라 곱셈을 빠르게 수행하기 위한 알고리즘 두 개를 제안한다. 하나는 서로 다른 두 수의 모듈라 곱셈 알고리즘이고, 다른 하나는 모듈라 제곱을 빠르게 수행하는 알고리즘이다. 이 둘은 기존의 모듈라 곱셈 알고리즘들에 비해 각각 절반과, l/3가량의 단정도 곱셈(single-precision multiplication)만을 필요로 한다. 실제로 PC상에서 구현한 결과 각각 100%와 30%의 속도향상을 보인다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.41-47
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• 2016

The times of multiplication for encryption and decryption of cryptosystem is primarily determined by implementation efficiency of the modular exponentiation of $a^b$(mod m). The most frequently used among standard modular exponentiation methods is a standard binary method, of which n-ary($2{\leq}n{\leq}6$) is most popular. The n-ary($1{\leq}n{\leq}6$) is a square-and-multiply method which partitions $b=b_kb_{k-1}{\cdots}b_1b_{0(2)}$ into n fixed bits from right to left and squares n times and multiplies bit values. This paper proposes a variable-length partition algorithm that partitions $b_{k-1}{\cdots}b_1b_{0(2)}$ from left to right. The proposed algorithm has proved to reduce the multiplication frequency of the fixed-length partition n-ary method.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.42-46
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• 2010

Encapsulation for information security is often carried out in Galois field in the form of arithmetic operations. This paper proposes how to efficiently perform exponentiation of arithmetic information on Galois field. Especially, by improving an existing bit-parallel exponentiator to exclude elements with heavy gate counts and to take advantage of system constants, this paper proposes how to implement a VLSI architecture with high performance even for large m.

• Journal of Digital Convergence
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• v.19 no.12
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• pp.339-345
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• 2021

In this paper, estimation angle performance analysis of amplitude-comparison monopulse radar under additive noise effect is dealt with. When uncorrelated white noises are added to the squinted beams, the angle estimation performance is analyzed through the mean square error(MSE). The numerical integration-based mean square error result completely overlaps the Monte Carlo-based mean square error result, which corresponds to 99.8% of the Monte Carlo-based mean square error result. In addition, the mean square error analysis method based on numerical integration has a much faster operation time than the mean square error method based on Monte Carlo. the angle estimation performance of the amplitude comparison monopulse radar can be efficiently analyzed in various noise environments through the proposed numerical integration-based mean square error method.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.10 no.4
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• pp.3-11
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• 2000

In this paper, we design modular multiplication systolic array and exponentiation processor having n bits message black. This processor uses Montgomery algorithm and LR binary square and multiply algorithm. This processor consists of 3 divisions, which are control unit that controls computation sequence, 5 shift registers that save input and output values, and modular exponentiation unit. To verify the designed exponetion processor, we model and simulate it using VHDL and MAX+PLUS II. Consider a message block length of n=512, the time needed for encrypting or decrypting such a block is 59.5ms. This modular exponentiation unit is used to RSA cryptosystem.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.867-873
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• 2014

Since the computation of a multiplicative inverse using MONB includes many squarings and thus calculating inverse is expensive, we, in this paper, propose a low cost inverse algorithm requiring $nb(2^nm-1)+w(2^nm-1)-2$ multiplications and $2^n-1$ squarings to compute an inverse in $GF(2^{2^nm})^*$ using special normal basis over $GF(2^{2^n})$, and give some implementation results using the algorithm and, show that the timing results of our implementation is faster than that of Itoh et al.'s method.