• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2004.10a
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• pp.223-226
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• 2004

The objectives of this study are to evaluate mechanical properties of glass ceramic for dome port cover material o( the ramjet. Candidate material for dome port cover of the ramjet is selected the machinable glass ceramic(MACOR glass-filled ceramic, Corning Glass Works, code 9658). Static and dynamic fracture toughness tests were performed to evaluate the apparent fracture toughness of notched specimen.

• Composites Research
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• v.29 no.2
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• pp.53-59
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• 2016

Aircraft wing structure is used as a fuel tank containing the fluid. Fuel tank and joint parts are consists of composite structure. Hydrodynamic Ram(HRAM) effect occurs when the high speed object pass through the aircraft wing or explosion and the high pressure are generated in the fuel tank by HRAM effect. High pressure can cause failure of the fuel tank and the joint parts as well as the aircraft wing structure. To ensure the aircraft survivability design, we shall examine the behavior of the joint parts in HRAM effect. In this study, static tensile tests were conducted on four kind of the composite T-Joints. The failure behavior of the composite T-joint was examined by strain gauges and high speed camera. We examine the validity of the Finite Element Modeling by comparing the results of FEA and static tensile tests. The failure stresses and failure pressure of the composite T-Joint were calculated by FEA.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• v.y2005m4
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• pp.112-115
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• 2005

The objectives of this study are to evaluate the dynamic fracture toughness of advance glass ceramics(MACOR glass-filled ceramic, Corning Glass Works) for dome port cover of the ramjet. Static and dynamic fracture toughness tests are performed using strain gage method in the variation of notch radii.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1037-1043
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• 2020

This paper presents a new Physical Unclonable Function (PUF) security chip based on a low-cost, small-area, and low-power semiconductor process for IoT devices. The proposed security circuit has multiple challenge-to-response pairs (CRP) by adding the switching circuit to the cross-coupled path between two inverters of the SRAM structure and applying the challenge input. As a result, the proposed structure has multiple CRPs while maintaining the advantages of fast operating speed and small area per bit of the conventional SRAM based PUF security chip. In order to verify the performance, the proposed switched SRAM based PUF security chip with a core area of 0.095㎟ was implemented in a 180nm CMOS process. The measurement results of the implemented PUF show 4096-bit number of CRPs, intra-chip Hamming Distance (HD) of 0, and inter-chip HD of 0.4052.