• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.21 no.3
• /
• pp.18-29
• /
• 2022

Recently, cooperative intelligent transport systems (C-ITS) testbeds have been deployed in great numbers, and advanced autonomous driving research using V2X communication technology has been conducted actively worldwide. In particular, the broadcasting services in their beginning days, giving warning messages, basic safety messages, traffic information, etc., gradually developed into advanced network services, such as platooning, remote driving, and sensor sharing, that need to perform real-time. In addition, technologies improving these advanced network services' throughput and latency are being developed on many fronts to support these services. Notably, this research analyzed the network latency requirements of the advanced network services to develop a remote driving service for the droid type low-speed robot based on the 3GPP C-V2X communication technology. Subsequently, this remote driving service's performance was evaluated using system modeling (that included the operator behavior) and simulation. This evaluation showed that a respective core and access network latency of less than 30 ms was required to meet more than 90 % of the remote driving service's performance requirements under the given test conditions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4B
• /
• pp.646-680
• /
• 2000

In this paper, we discuss the design and implementation of a concurrency control manager for a main memory DBMS(MMDBMS). Since an MMDBMS, unlike a disk-based DBMS, performs all of data update or retrieval operations by accessing main memory only, the portion of the cost for concurrency control in the total cost for a data update or retrieval is fairly high. Thus, the development of an efficient concurrency control manager highly accelerates the performance of the entire system. Our concurrency control manager employs the 2-phase locking protocol, and has the following characteristics. First, it adapts the partition, an allocation unit of main memory, as a locking granule, and thus, effectively adjusts the trade-off between the system concurrency and locking cost through the analysis of applications. Second, it enjoys low locking costs by maintaining the lock information directly in the partition itself. Third, it provides the latch as a mechanism for physical consistency of system data. Our latch supports both of the shared and exclusive modes, and maximizes the CPU utilization by combining the Bakery algorithm and Unix semaphore facility. Fourth, for solving the deadlock problem, it periodically examines whether a system is in a deadlock state using lock waiting information. In addition, we discuss various issues arising in development such as mutual exclusion of a transaction table, mutual exclusion of indexes and system catalogs, and realtime application supports.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.8B
• /
• pp.473-481
• /
• 2007

We are interested in the PON which is easy to install and inexpensive to maintain, as it is a solution of the FTTH that is a core technology of the BcN access network. When a new ONU is connected, TDMA PON has a procedure called ranging that OLT measures the distance and allocates the equalized delay to it in order to provide the same logical distance to all ONUs. For the procedure, the OLT has to open a time window several times and already activated ONUs cannot transmit a data to the upstream during the periods. Accordingly, it is important to reduce the window size for saving the bandwidth and providing a user the service smoothly. In this paper, we investigate the ONU activation method of G-PON based on ITU-T G984.3 and suggest an advanced method(algorithm I) that minimizes the window size without information of ONU distance. The size can be reduced by calculating the pre-assigned delay obtained during Serial number state. Also, we compare it with another(algorithm II) with information of distance. As a result, the window size reduces to $50{\sim}90%$ for the algorithm I and 99% for algorithm II during the ONU activation process.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.1
• /
• pp.11-23
• /
• 2014

Wireless Mesh Network(WMN) has drawn much attention due to easy deployment and good scalability. Recently, major power utilities have been focusing on R&D to apply WMN technology in Smart Grid Network. Smart Grid is an intelligent electrical power network that can maximize energy efficiency through bidirectional communication between utility providers and customers with ICT(Information Communication Technology). It is necessary to guarantee QoS of some important data in Smart Grid system such as real-time data delivery. In this paper, we suggest QoS enhancement method for WMN based Smart Grid system using IEEE 802.11s. We analyze Smart Grid Application characteristics and apply IEEE 802.11s WMN scheme for Smart Grid in domestic power communication system. Performance evaluation is progressed using NS-2 simulator implementing IEEE 802.11s. The simulation results show that the QoS enhancement scheme can guarantee stable bandwidth irrespective of traffic condition due to IEEE 802.11s reservation mechanism.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.11
• /
• pp.32-40
• /
• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.

• The KIPS Transactions:PartD
• /
• v.14D no.1 s.111
• /
• pp.21-34
• /
• 2007

According to recent rapid price drop and capacity growth of main memory, the number of applications on main memory databases is dramatically increasing. Cache miss, which means a phenomenon that the data required by CPU is not resident in cache and is accessed from main memory, is one of the major causes of performance degradation of main memory databases. Several cache-conscious trees have been proposed for reducing cache miss and making the most use of cache in main memory databases. Since each cache-conscious tree has its own unique features, more than one cache-conscious tree can be used in a single application depending on the application's requirement. Moreover, if there is no existing cache-conscious tree that satisfies the application's requirement, we should implement a new cache-conscious tree only for the application's sake. In this paper, we propose the cache-conscious generalized search tree (CC-GiST). The CC-GiST is an extension of the disk-based generalized search tree (GiST) [HNP95] to be tache-conscious, and provides the entire common features and algorithms in the existing cache-conscious trees including pointer compression and key compression techniques. For implementing a cache-conscious tree based on the CC-GiST proposed in this paper, one should implement only a few functions specific to the cache-conscious tree. We show how to implement the most representative cache-conscious trees such as the CSB+-tree, the pkB-tree, and the CR-tree based on the CC-GiST. The CC-GiST eliminates the troublesomeness caused by managing mire than one cache-conscious tree in an application, and provides a framework for efficiently implementing arbitrary cache-conscious trees with new features.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.4
• /
• pp.947-960
• /
• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.4
• /
• pp.913-920
• /
• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• The KIPS Transactions:PartD
• /
• v.12D no.2 s.98
• /
• pp.233-246
• /
• 2005

To enhance the user response time of content-based retrieval service for multimedia information, several multi-dimensional index schemes have been proposed. M-tree, a well-known multidimensional index scheme is of metric space access method, and is based on the distance between objects in the metric space. However, since the overlap between index spaces of nodes might enlarge the number of nodes of M-tree accessed for query processing, the user response time for content-based multimedia information retrieval grows longer. In this paper, we propose a node split algorithm which is able to reduce the sire of overlap between index spaces of nodes in M-tree. In the proposed scheme, we choose a virtual center point as the routing object and entry redistribution as the postprocessing after node split in order to reduce the radius of index space of a node, and finally in order to reduce the overlap between the index spaces of routing nodes. From the experimental results, we can see the proposed split algorithm reduce the overlap between index space of nodes and finally enhance the user response time for similarity-based query processing.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.3
• /
• pp.461-467
• /
• 2003

This paper proposes the method of mobility implementation for location searching in the intelligence wireless ATM networks that expand and apply standard broadband signaling capabilities, and analyze the performance based on the numerical algorithm. The existing B-ISDN UNI protocol stack demands the location search mechanism to determine the location of mobile terminal in the wireless ATM networks because it use single protocol through the fixed PTP interface or PTM interface that don't support terminal mobility. The proposed method make possible the dynamic mobility at a part of wireless access by minimizing the signaling load without a falling-off in system performance by using the intelligence network technology according to the expansion of ATM and B-ISDN signaling integration based on the fixed networks. We implemented the performance analysis by MFC modeling based on numerical algorithm, and realized the efficiency of expenses by carrying out the comparative signaling performance evaluation to measure the relative gains of location search service in the intelligence wireless ATM system. The obtained results have the flexibility to operate in the public B-ISDN network environment without a change of existing B-ISDN/ATM NNI signaling reference to support the wireless ATM access system, and can easily expand to correspond to terminal mobility and various multimedia services in the next broadband PCS.