• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.75-87
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• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.163-163
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• 2010

중적외선 영역 ($3{\sim}5\;{\mu}m$)은 공기 중에 존재하는 이산화탄소나 수증기에 의해 흡수가 일어나지 않기 때문에 군사적으로 중요한 파장 영역이며, 야간에 적을 탐지하는데 응용되고 있다. InSb는 77 K에서 중적외선 파장 흡수에 적합한 밴드갭 에너지 (0.228 eV)를 갖고 있으며, 다른 화합물 반도체와 달리 전하 수송자 이동도 (전자: $10^6\;cm^2/Vs$, 정공: $10^4\;cm^2/Vs$)가 매우 빠르기 때문에 적외선 화상 감지기 재료로 매우 적합하다. 또한 현재 중적외선 영역대에서 널리 사용되는 HgCdTe (MCT)와 대등한 소자 성능을 나타냄과 동시에 낮은 기판 가격, 소자의 제작 용이성 때문에 MCT를 대체할 물질로 주목 받고 있다. 하지만, 기판과 절연막의 계면에 존재하는 결함 때문에 에너지 밴드갭 내에 에너지 준위를 형성하여 높은 누설 전류 특성을 보인다. 따라서 InSb 적외선 소자의 구현을 위하여 고품질의 절연막의 연구가 필수적이라고 할 수 있겠다. 절연막의 특성을 알아보기 위해, n형 InSb 기판에 플라즈마 화학 기상 증착법 (PECVD)을 이용하여 $SiO_2$, $Si_3N_4$를 증착하였으며, 증착 온도를 $120^{\circ}C$에서 $240^{\circ}C$까지 $40^{\circ}C$ 간격으로 변화하여 증착온도가 미치는 영향에 대하여 알아보았다. 절연막과 기판의 계면 특성을 분석하기 위하여 77 K에서 커패시턴스-전압 (C-V) 분석을 하였으며, 계면 트랩 밀도는 Terman method를 이용하여 계산하였다 [1]. $Si_3N_4$를 증착하였을 경우, $120{\sim}240^{\circ}C$의 증착 온도에서 $2.4{\sim}4.9{\times}10^{12}\;cm^{-2}eV^{-1}$의 계면 트랩 밀도를 가졌으며, 증착 온도가 증가할수록 계면 트랩 밀도가 증가하는 경향을 보였다. 또한 모든 증착 온도에서 flat band voltage가 음의 전압으로 이동하였다. $SiO_2$의 경우 $120{\sim}200^{\circ}C$의 증착온도에서 $7.1{\sim}7.3{\times}10^{11}\;cm^{-2}eV^{-1}$의 계면 트랩 밀도 값을 보였으나, $240^{\circ}C$ 이상에서 계면 트랩밀도가 $12{\times}10^{11}\;cm^{-2}eV^{-1}$로 크게 증가하였다. $SiO_2$ 절연막을 사용함으로써, $Si_3N_4$ 대비 약 25% 정도 낮은 계면 트랩 밀도를 얻을 수 있었으며, 모든 증착 온도에서 양의 전압으로 flat band voltage가 이동하였다. 두 절연막에 대한 계면 트랩의 원인을 분석하기 위하여 XPS 측정을 진행하였으며, 깊이에 따른 조성 분석을 하였다. 본 실험에서 최적화된 $SiO_2$ 절연막을 이용하여 InSb 소자의 pn 접합 연구를 진행하였다. Be+ 이온 주입을 진행하고, 급속열처리(RTA) 공정을 통하여 p층을 형성하였다. -0.1 V에서 16 nA의 누설 전류 값을 보였으며, $2.6{\times}10^3\;{\Omega}\;cm^2$의 RoA (zero bias resistance area)를 얻을 수 있었다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.12
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• pp.513-518
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• 2019

Friction Stir Welding is a welding technique for metal materials that utilizes the heat generated by friction between the material to be welded and the welding tool that rotates at high speed. In this study, a numerical analysis method was used to analyze the change in the internal temperature of the welded material during friction stir welding. As the welding target material, AZ31 magnesium alloy was applied and the welding phenomenon was considered a flow characteristic, in which a melting-pool was formed. FLUENT was used as the numerical tool to perform the flow analysis. For flow analysis of the welding process, the welding material was assumed to be a high viscosity Newtonian fluid, and the boundary condition of the welding tool and the material was considered to be the condition that friction and slippage occur simultaneously. Analyses were carried out for various rotational speeds and the translational moving speed of the welding tool as variables. The analysis results showed that the higher the rotational speed of the welding tool and the slower the welding tool movement speed, the higher the maximum temperature in the material increases. Moreover, the difference in the rotational speed of the welding tool has a greater effect on the temperature change.

• Journal of Sensor Science and Technology
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• v.10 no.5
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• pp.292-303
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• 2001

This work reports the tunneling effects of the lateral field emitters. Tunneling effect is applicable to the VMFS(vacuum magnetic field sensors). VMFS uses the fact that the trajectory of the emitted electrons are curved by the magnetic field due to Lorentz force. Polysilicon was used as field emitters and anode materials. Thickness of the emitter and the anode were $2\;{\mu}m$, respectively. PSG(phospho-silicate-glass) was used as a sacrificial layer and it was etched by HF at a releasing step. Cantilevers were doped with $POCl_3(10^{20}cm^{-3})$. $2{\mu}m$-thick cantilevers were fabricated onto PSG($2{\mu}m$-thick). Sublimation drying method was used at releasing step to avoid stiction. Then, device was vacuum sealed. Device was fixed to a sodalime-glass #1 with silver paste and it was wire bonded. Glass #1 has a predefined hole and a sputtered silicon-film at backside. The front-side of the device was sealed with sodalime-glass #2 using the glass frit. After getter insertion via the hole, backside of the glass #1 was bonded electrostatically with the sodalime-glass #3 at $10^{-6}\;torr$. After sealing, getter was activated. Sealing was successful to operate the tunneling device. The packaged VMFS showed very small reduced emission current compared with the chamber test prior to sealing. The emission currents were changed when the magnetic field was induced. The sensitivity of the device was about 3%/T at about 1 Tesla magnetic field.

• Journal of Sensor Science and Technology
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• v.9 no.1
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• pp.1-8
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• 2000

One of today's very critical and sensitive accurate accelerometer which can be used higher temperature than $200^{\circ}C$ and corrosive environment, is particularly demanded for automotive engine. Because silicon is a material of large temperature dependent coefficient, and the piezoresistors are isolated with p-n junctions, and its leakage current increase with temperature, the performance of the silicon accelerometer degrades especially after $150^{\circ}C$. In this paper, The temperature characteristic of a accelerometer using silicon on insulator (SOI) structure is studied theoretically, and compared with experimental results. The temperature coefficients of sensitivity and offset voltage (TCS and TCO) are related to some factors such as thermal residual stress, and are expressed numerically. Thermal stress analysis of the accelerometer has also been carried out with the finite-element method(FEM) simulation program ANSYS. TCS of this accelerometer can be reduced to control the impurity concentration of piezoresistors, and TCO is related to factors such as process variation and thermal residual stress on the piezoresistors. In real packaging, The avarage thermal residual stress in the center support structure was estimated at around $3.7{\times}10^4Nm^{-2}^{\circ}C^{-1}$ at sensing resistor. The simulated ${\gamma}_{pT}$ of the center support structure was smaller than one-tenth as compared with that of the surrounding support structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1448-1452
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• 2004

In this paper, a photodiode capable of obtaining a sufficient photo/ dark current ratio at both a forward bias state and a reverse bias state is proposed. The photodiode includes a glass substrate, an Cr thin film formed as a lower electrode over the glass substrate, Cr silicide thin film(∼l00$\AA$) ) formed as a schottky barrier over the Cr thin film, a hydrogenated amorphous silicon film formed as a photo conduction layer over a portion of the Cr silicide thin film. Transparent conduction film ITO (thickness 100nm) formed as an upper electrode over the hydro-generated amorphous silicon film is then deposited in pure argon at room temperature for the Schottky contact and light window. The high quality Cr silicide thin film using annealing of Cr and a-Si:H is formed and analyzed by experiment. We have obtained the film with a superior characteristics. The dark current of the ITO/a-Si:H Schottky at a reverse bias of -5V is ∼3$\times$IO-12 A/un2, and one of the lowest reported, hitherto. AES(Auger Electron Spectroscophy) measurements indicate that this notable improvement in device characteristics stems from reduced diffusion of oxygen, rather than indium, from the ITO into the a-Si:H layer, thus, preserving the integrity of the Schottky interface. The spectral response of the photodiode for wavelengths in the range from 400nm to 800nm shows the expected behavior whereby the photocurrent is governed by the absorption characteristics of a-Si:H.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.9-15
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• 2007

In this paper, we present the design of Schottky diodes and voltage multiplier for UHF-band passive RFID applications. The Schottky diodes were fabricated using Titanium (Ti/Al/Ta/Al)-Silicon (n-type) junction in $0.35\;{\mu}m$ CMOS process. The Schottky diode having $4{\times}10{\times}10\;{\mu}m^{2}$ contact area showed a turn-on voltage of about 150 mV for the forward diode current of $20\;{\mu}A$. The breakdown voltage is about -9 V, which provides sufficient peak inverse voltage necessary for the voltage multiplier in the RFID tag chip. The effect of the size of Schottky diode on the turn-on voltage and the input impedance at 900 MHz was investigated using small-signal equivalent model. Also, the effect or qualify factor of the diode on the input voltage to the tag chip is examined, which indicates that high qualify factor Schottky diode is desirable to minimize loss. The fabricated voltage multiplier resulted in a output voltage of more than 1.3 V for the input RF signal of 200mV, which is suitable for long-range RFID applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.71-80
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• 2007

This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

• Journal of Adhesion and Interface
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• v.18 no.1
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• pp.25-32
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• 2017

For application to display module junction process, the silk screen printing based on UV curable acrylic pressure sensitive adhesive(PSA) with silica nano-particles and the rheological properties were studied to investigate the effect on printability and adhesion. The monomers for PSA were based on 2-ethylhexyl acrylate(2-EHA) and acrylic acid(AA) 93:7, butyl acylate(BA), 2-hydroxyethyl acrylate(2-HEA) and tetrahydrofurfuryl acrylate(THFA) were added. Additionally, hydrophobic and hydrophilic nano-particles AEROSIL R974 and AEROSIL 200 were added, respectively. When the ratio of nano-particle was used above 4 or 7 phr, G' and ${\eta}^*$ were increased significantly. When the ratio of AEROSIL 200 was used above 7 phr, the penetration property was decreased during the silk screen printing. We found that the adhesion was decreased with increasing the nano-particle content, and it was decreased in the case of the hydrophilic nano-particle AEROSIL 200.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.39-43
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• 2009

In this paper, the flow characteristics of underfill material driven by capillary action between flip-chip and substrate were investigated. Also, the effects of viscosity level and dispensing point of underfill on flow characteristics were investigated. Flip chip package size was $5mm{\times}5mm{\times}0.65^tmm$, the diameter of solder bump was 100 ${\mu}m$, and the pitch was 150 ${\mu}m$. It was full grid area-array type with 1024 I/Os. The glass substrate was used and the gap between the chip and substrate was 50 ${\mu}m$. For the experimental study, three different underfills with different viscous properties($2000{\sim}3700$ cps), and two different types of dispensing methods(center dot and edge dot) were used. The flow characteristics and filling time of underfill were investigated by using CCD camera. The results show that the edge flow was faster than center flow due to the edge effect, which was caused by the resistance of solder bumps. In case of edge dot dispensing type, the filling time was faster due to the large edge effect, compared to center dot dispensing type. Also, it was found that the underfill flow was faster and the filling time decreased as the viscosity level of underfill was decreased.