• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.35-40
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• 2010

In this paper, we propose a hardware resource sharable camera control processor (CCP) for low-cost and low-power camera cell phones. The main idea behind the proposed architecture is that adds direct access paths in the CCP to share its hardware resources so that the baseband processor expands its capabilities and boosts its performance by utilizing CCF's hardware resources. In addition, we applied a module grain dock-gating method to reduce power dissipation. Hence, the CCP can realize low-power and low-cost camera cell phones with greater hardware efficiency. This chip was fabricated in a 0.18um CMOS process with an active area of $3.8mm\;{\times}\;3.8mm$.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.249-249
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• 2010

핵융합로에서는 디버터의 열부하에 대한 안전성을 고려하기 위해 열전도도 및 열 저항성이 높은 텅스텐이 대면 물질로 고려되고 있으며, 경제적인 측면과 실용성 측면에서 텅스텐블록을 직접 제작하여 사용하는 것보다 텅스텐코팅이 효과적이라는 의견이 지배적이다. 또한 ASDEX Upgrade 에서는 탄소블럭에 텅스텐을 코팅하여 챔버 외벽 및 디버터 영역까지 구성하여 캠페인을 진행하였고, 재료적인 측면에서 안정성을 확인 하였다. 따라서 본 연구에서는 디버터 및 챔버외벽 등에 대한 대면물질을 구성하기 위해 상압 열플라즈마 제트를 이용하여 고온에서의 용융 및 냉각을 통해 모재에 텅스텐 피막을 적층하는 과정을 수행하고 있다. 기존의 연구를 통해 일부 공정 변수에 대해서는 이미 적정한 범위의 공정조건을 확보하였고, 기공도와 산화도 및 부착력 등의 물성치에 대한 추가적인 향상을 위해 주요 공정 변수에 집중하여 최적의 조건을 탐색하는 과정이 진행 중이다. 이를 위해 출력증가실험의 일환으로서 기존 36kW급 플라즈마 토치 전력을 한 단계 끌어 올려 48kW급 전력까지 단계적으로 상승시킴으로써 이에 따른 물성치 변화를 검증하고 있다. 현재 44kW 급까지 실험이 수행되었으며, 이를 통해 공극률 감소 및 미세구조 변화에 대한 결과를 얻었다. 실제로 토치의 출력을 증가시킴으로서 텅스텐 피막의 물성치가 변화하는 메커니즘은 플라즈마 제트의 중심부 온도 및 축방향 속도에 의해 결정된다. 중심부 온도가 상승하게 될수록 코팅을 위해 분사되는 분말의 용융률은 증가하지만 분말 외벽에 산화텅스텐이 형성될 가능성은 증가하게 되며, 플라즈마 제트의 모재를 향상 축방향 속도가 증가할수록 용융 된 분말이 모재에 증착 시 형성하는 형태가 원형에 가깝게 되므로 기공이 감소하는 효과가 발생한다. 특히 용융된 분말의 증착 형태는 모재의 온도 및 분말의 입사속도에 결정적이 영향을 받게 되며, 결국 모재와 분말사이의 습윤성에 의한 분말 분산속도가 분말의 입사속도에 버금갈 경우 분말은 모재 위에서 효과적으로 원형으로 전이하며 적층하게 된다. 이러한 전이 현상은 앞에서 언급한 모재의 온도 등에 의해 결정적으로 영향을 받게 되며, 모재의 온도가 전이온도 이하일 경우 폭파형태에서 원형으로 분말의 증착 형태가 전이하게 된다. 이외에 추가적으로 진행하고 있는 연구는 코팅 전처리에 해당하는 분말 효과이며, 특히 탄화텅스텐 분말을 통한 재료적 auto-shroud 효과와 미세분말을 이용한 분말 표면열속의 증가에 따른 용융률 증가효과를 연구에 포함할 계획이다. 이러한 연구는 열적, 그리고 재료적 해석을 바탕으로 해석적 접근을 통해 이루어진다.

• Journal of KIISE
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• v.42 no.4
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• pp.427-433
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• 2015

The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.4
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• pp.141-146
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• 2015

Data have been increased enormously due to the development of IT technology such as recent smart equipments, social network services and streaming services. To meet these environments the technologies that can treat mass data have received attention, and the typical one is Hadoop. Hadoop is on the basis of open source, and it has been designed to be used at general purpose computers on the basis of Linux. To initial Hadoop nearly no security was introduced, but as the number of users increased data that need security increased and there appeared new version that introduced Kerberos and Token system in 2009. But in this method there was a problem that only one secret key can be used and access permission to blocks cannot be authenticated to each user, and there were weak points that replay attack and spoofing attack were possible. Hence, to supplement these weak points and to maintain efficiency a protocol on the basis of group key, in which users are authenticated in logical group and then this is reflected to token, is proposed in this paper. The result shows that it has solved the weak points and there is no big overhead in terms of efficiency.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.315-321
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• 2011

The CRT monitor display system for SONAR signal that are commonly used in ships or naval vessels uses vector scanning method. Therefore the processing circuits of the system is complex. Also because production had been shut down, the supply of parts is difficult as well as high-cost. FPGA -based embedded processor system is flexible to adapting to various applications because it makes simple processing circuits and its core is easily reconfigurable, and provides high speed performance in low-cost. In this paper, we describe an implementation of SONAR signal LCD display system using the FPGA embedded processor system to overcome some weakness of existing CRT system. By changing X-Y Deflection and CRT control blocks of current system into FPGA embedded processor system, our system provides the simplicity, flexibility and low-cost of system configuration, and also real-time acquisition and display of SONAR signal.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.3
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• pp.39-49
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• 2003

The delta operator approach and the singular perturbation technique are introduced. The former reduces the round-off error in the numerical computation. The latter reduces computing time by decoupling the original system into the fast and slow sub-systems. The aircraft dynamics consists of the Phugoid and short-period motions whether its model is longitudinal or lateral. In this paper, an approximated solutions of lateral dynamic model of Beaver obtained by using those two methods in compared with the exact solution. For open-loop system and closed-loop system, and approximated solution gets identical to the exact solution with only one iteration and without iteration, respectively. Therefore, it is shown that implementing those approaches is very effective in the flight dynamic and control.

• Journal of the Korean Society for Library and Information Science
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• v.33 no.1
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• pp.87-111
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• 1999

This article investigates the functions, needs, and developments of the MARC format for classification data. and recommends the development for the KORMARC format for classification data. It ae analyzes the record structure, content designation and the content of it mainly based on USMARC format. Structure and content designation are almost same with those of the bibliographic and authority formats. The data fields divided into functional blocks based on their functions. Record contents of the data in the fixed-length fields include more elements on the classification numbers, including type of number, classification validity, standard or optional number, synthesized number. Variable fields can be grouped into several blocks, inducing those for numbers and codes: for classification numbers and terms; for references and tracings; for notes fields: for index terms fields, and for number building fields. Data in each fields of this format have the same contents with those in other related fields as soon as possible. This article analyzes the content in each data fields in detail.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• Journal of Internet Computing and Services
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• v.15 no.5
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• pp.17-24
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• 2014

Blind algorithms designed to maximize the probability that constant modulus errors become zero carry out some summation operations for a set of constant modulus errors at an iteration time inducing heavy complexity. For the purpose of reducing this computational burden induced from the summation, a new approach to the estimation of the zero-error probability (ZEP) of constant modulus errors (CME) and its gradient is proposed in this paper. The ZEP of CME at the next iteration time is shown to be calculated recursively based on the currently calculated ZEP of CME. It also is shown that the gradient for the weight update of the algorithm can be obtained by differentiating the ZEP of CME estimated recursively. From the simulation results that the proposed estimation method of ZEP-CME and its gradient produces exactly the same estimation results with a significantly reduced computational complexity as the block-processing method does.