• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.258-268
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• 2001

The compression method is necessarily used to send the high quality moving picture that contains a number of data in image processing. In the field of moving picture compression method, the motion estimation algorithm is used to reduce the temporal redundancy. Block matching algorithm to be usually used is distinguished partial search algorithm with full search algorithm. Full search algorithm be used in this paper is the method to compare the reference block with entire block in the search window. It is very efficient and has simple data flow and control circuit. But the bigger the search window, the larger hardware size, because large computational operation is needed. In this paper, we design the full search block matching motion estimator. Using the DCT DC values, we decide luminance. And we apply 3 bit compare-selector using bit plane to I(Intra coded) picture, not using 8 bit luminance signals. Also it is suggested that use the same selective bit for the P(Predicted coded) and B(Bidirectional coded) picture. We compare based full search method with PSNR(Peak Signal to Noise Ratio) for C language modeling. Its condition is the reference block 8$\times$8, the search window 24$\times$24 and 352$\times$288 gray scale standard video images. The result has small difference that we cannot see. And we design the suggested motion estimator that hardware size is proved to reduce 38.3％ for structure I and 30.7％ for structure II. The memory is proved to reduce 31.3％ for structure I and II.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.10-16
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• 2012

For high speed visual inspection in semiconductor industries, it is essential to acquire two-dimensional images on regions of interests with a large field of view (FOV) and a high resolution simultaneously. In this paper, an imaging system is newly proposed to achieve high quality image in terms of precision and FOV, which is composed of single lens, a beam splitter, two camera sensors, and stereo image grabbing board. For simultaneously acquired object images from two camera sensors, Zhang's camera calibration method is applied to calibrate each camera first of all. Secondly, to find a mathematical mapping function between two images acquired from different view cameras, the matching matrix from multiview camera geometry is calculated based on their image homography. Through the image homography, two images are finally registered to secure a large inspection FOV. Here the inspection system of using multiple images from multiple cameras need very fast processing unit for real-time image matching. For this purpose, parallel processing hardware and software are utilized, such as Compute Unified Device Architecture (CUDA). As a result, we can obtain a matched image from two separated images in real-time. Finally, the acquired homography is evaluated in term of accuracy through a series of experiments, and the obtained results shows the effectiveness of the proposed system and method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.1-9
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• 2007

For an efficient implementation of cryptosystems based on arithmetic in a finite field $GF(2^n)$, their hardware implementation is an important research topic. To construct a multiplier with low area complexity, the divide-and-conquer technique such as the original Karatsuba-Ofman method and multi-segment Karatsuba methods is a useful method. Leone proposed an efficient parallel multiplier with low area complexity, and Ernst at al. proposed a multiplier of a multi-segment Karatsuba method. In [1], the authors proposed new $MSK_5$ and $MSK_7$ methods with low area complexity to improve Ernst's method. In [3], the authors proposed a method which combines $MSK_2$ and $MSK_3$. In this paper we propose an efficient multiplication method by combining $MSK_2,\;MSK_3\;and\;MSK_5$ together. The proposed method reduces $116{\cdot}3^l$ gates and $2T_X$ time delay compared with Gather's method at the degree $25{\cdot}2^l-2^l with l>0.

• Journal of IKEEE
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• v.19 no.4
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• pp.596-602
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• 2015

In this paper, a unified inverse transformer is designed for HEVC and VP9. The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as $4{\times}4{\sim}32{\times}32$ HEVC IDCT, $4{\times}4$ HEVC IDST, $4{\times}4{\sim}32{\times}32$ VP9 IDCT, $4{\times}4{\sim}16{\times}16$ VP9 IADST and $4{\times}4$ IWHT. Same computations are used in HEVC IDCT and VP9 IDCT, except for the scales of the coefficients. Similarly, same computations are used in HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST, except for the scales of the coefficients. Furthermore, HEVC IDCT, VP9 IDCT, and VP9 IADST are the subsets of upper level IDCTs. The proposed architecture reuses multipliers when the computation is identical. Also it shares adders and butterfly structures even when the multiplier coefficients are different. So it reduces the hardware size significantly. Synthesized in 0.18 um technology, the gate count is 456,442 gates. which achieved 22.6% reduction compared to conventional architectures.

• Journal of IKEEE
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• v.19 no.2
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• pp.193-200
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• 2015

In this paper, we propose the radiation measuring algorithm and the device composition using CMOS image sensor. The radiation measuring algorithm using CMOS image sensor is based on the radiation particle distinguishing algorithm projected to the CMOS image sensor and accumulated and average number of pixels of the radiation particles projected to dozens of images per second with CMOS image sensor. The radiation particle distinguishing algorithm projected to the CMOS image sensor measures the radiation particle images by dividing them into R, G and B and adjusting the threshold value that distinguishes light intensity and background from the particle of each image. The radiation measuring algorithm measures radiation with accumulated and average number of radiation particles projected to dozens of images per second with CMOS image sensor according to the preset cycle. The hardware devices to verify the suggested algorithm consists of CMOS image sensor and image signal processor part, control part, power circuit part and display part. The test result of radiation measurement using the suggested CMOS image sensor is as follows. First, using the low-cost CMOS image sensor to measure radiation particles generated similar characteristics to that from measurement with expensive GM Tube. Second, using the low-cost CMOS image sensor to measure radiation presented largely similar characteristics to the linear characteristics of expensive GM Tube.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• The Journal of Society for e-Business Studies
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• v.20 no.3
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• pp.89-112
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• 2015

Recently, the business environment of healthcare has changed rapidly due to the entering the mobile era, the intensifying global competition, and the explosion of healthcare needs. Despite of necessity in expanding new IT-based medical services and investing IT resources to respond environmental changes, the small and medium sized hospitals could not realize these requirements due to the limited management resources. CHISSMH is designed and presented in this research to provide high valued clouding medical services with reasonable price. CHISMH is designed and presented in this research to provide high valued medical services with reasonable price through cloud computing. CHISME is designed to maximize resource pooling and sharing through the visualization. By doing so, Cloud Service provider could minimize maintenance cost of cloud data center, provide high level services with reasonable pay-per-use price. By doing so, Cloud Service provider could minimize maintenance cost of cloud data center, and could provide high level services with reasonable pay-per-use price. CHISME is expected to be base framework of cloud HIS services and be diffusion factor of cloud HIS services Operational experience in CHISSMH with 15 hospitals is analyzed and presented as well.

• Journal of the Korea Society of Computer and Information
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• v.18 no.12
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• pp.55-64
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• 2013

In this paper, the HILS (Hardware In-the-Loop Simulation) system to analyze and to verify the performance of the targeting pod is addressed. The main functions of the targeting pod is acquiring and tracking targets to guide a LGB (Laser Guided Bomb) to the targets. For the analysis of targeting pod, the real time simulate images generation of IR and daylight cameras, sever control technology, and the analysis of laser transfer characteristics are necessary. For the real time image generation and the laser transfer characteristics analysis, off-the-shelf SDK(Software Development Kit) OKTAL-SE is used. For the servo controller, well-proven mechanism in the previous program is applied to increase servo control accuracy. To analyze the performance of a targeting pod in a realistic environment, 1553B, ARINK818 interface and etc. which are actually implemented in real combat aircrafts are applied in the system. By using the developed HILS system, the performance of currently operating targeting pods in real combat aircrafts can be analyzed and predicted. Additionally, the relationship between overall system performance and each module performance can be analyzed, the currently developed HILS system is expected to be a very useful tool to generate system development requirements of targeting pods and to reduce any possible future development risks.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.273-281
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• 2019

The energy consumed by buildings among the total national energy consumption is more than 10% of the total. For this reason, Korea has adopted the zero energy building policy since 2025, and research on the energy saving technology of buildings has been demanded. Analysis of buildings' energy consumption patterns shows that lighting, heating and cooling energy account for more than 60% of total energy consumption, which is directly related to solar power acquisition and window opening and closing operation. In this paper, we have developed a low - power IoT sensor module for window system to transfer acquired information to building energy management system. This module transmits the external environment and window opening / closing status information to the building energy management system in real time, and constructs the network to actively take energy saving measures. The power used in the module is designed as an independent power source using solar power among the harvest energy. The topology of the power supply is a Buck converter, which is charged at 4V to the lithium ion battery through MPPT control, and the efficiency is about 85.87%. Communication is configured to be able to transmit in real time by applying WiFi. In order to reduce the power consumption of the module, we analyzed the hardware and software aspects and implemented a low power IoT sensor module.