• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.3-6
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• 2012

최근 응용 특화된 다양한 구조의 프로세서가 확산됨에 따라 기존 운영체제를 다른 구조의 플랫폼으로 이식하는 비용이 증가하고 있다. 기존 운영체제에서는 소스 코드 수준에서 하드웨어 의존적인 부분을 HAL(hardware abstraction layer)로 구분하여 관리함으로써 이기종 플랫폼간의 이식성을 높이고자 하였다. 그러나 기존 HAL 구조는 대부분 하드웨어의 물리적인 구조만을 고려하여 설계되어 체계적인 이식 작업이 어렵다는 문제점을 가지고 있다. 이를 위해 본 논문에서는 하드웨어의 물리적인 구조와 운영체제의 기능적인 요소를 함께 고려한 HAL 구조를 제안한다. 제안하는 HAL 구조의 효용성은 S3C2410 에서 실행하는 운영체제를 Cell BE 플랫폼으로 이식하는 사례 연구를 통해 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.457-458
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• 2021

딥러닝 알고리즘 중 DCNN(DeConvolutional Neural Network)은 이미지 업스케일링과 생성·복원 등 다양한 분야에서 뛰어난 성능을 보여주고 있다. DCNN은 많은 양의 데이터를 병렬로 처리할 수 있기 때문에 하드웨어로 설계하는 것이 유용하다. 최근 DCNN의 하드웨어 구조 연구에서는 overlapping sum 문제를 해결하기 위해 deconvolution 필터를 convolution 필터로 변환하는 TDC(Transforming the Deconvolutional layer into the Convolutional layer) 알고리즘이 제안되었다. 하지만 TDC를 CPU(Central Processing Unit)로 수행하기 때문에 연산의 최적화가 어려우며, 외부 메모리를 사용하기에 추가적인 전력이 소모된다. 이에 본 논문에서는 저전력으로 구동할 수 있는 FPGA 기반 TDC 하드웨어 구조를 제안한다. 제안하는 하드웨어 구조는 자원 사용량이 적어 저전력으로 구동 가능할 뿐만 아니라, 병렬 처리 구조로 설계되어 빠른 연산 처리 속도를 보인다.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.103-106
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• 2010

전자 출판 기술과 전자책 단말기의 발전으로 전자책 컨텐츠의 보급이 확산되면서 전자책은 정보 자료로써 그 중요성이 더해가고 있으며 전자책 단말기를 통하여 컨텐츠를 다운로드 받으려는 요구가 증가 되어 가고 있다. 전자책 컨텐츠 다운로드 서버를 개발하기 위해서는 전자책 단말기의 하드웨어 특성이 고려되어야 한다. 본 논문에서는 Wi-Fi 전자책 단말기의 하드웨어 특성을 고려하여 Wi-Fi 전자책 단말기를 통해 전자책 컨텐츠를 효과적으로 다운 받을 수 있는 다운로드 서버를 설계 및 구현 하였다.

• KIPE Magazine
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• v.12 no.3
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• pp.25-31
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• 2007

• Journal of Korean Electronics
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• v.4 no.3
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• pp.76-81
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• 1984

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• Journal of Aerospace System Engineering
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• v.16 no.4
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• pp.10-16
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• 2022

Since aviation systems are developed as the complex form of software a hardware, the necessity to apply to relevant guidelines is increasing. It is however uncommon that international development guidelines regarding electronic hardware are applied to current domestic aviation systems. In this paper, we compare and analyze DO-254 and ECSS-Q-ST-60-02C, electronic hardware development guidelines with the case of KASS (Korea Augmentation Satellite System) Performance Suitability, based on the project of SBAS (Satellite Based Augmentation System) development and construction.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.90-97
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• 2006

In this paper, we present a cost-effective architecture of high-speed soft-decision Viterbi decoder for Multi-band OFDM(MB-OFDM) systems. In the design of modem for MB-OFDM systems, a parallel processing architecture is general]y used for the reliable hardware implementation, because the systems should support a very high-speed data rate of at most 480Mbps. A Viterbi decoder also should be designed by using a parallel processing structure and support a very high-speed data rate. Therefore, we present a optimized hardware architecture for 4-way parallel processing Viterbi decoder in this paper. In order to optimize the hardware of Viterbi decoder, we compare and analyze various ACS architectures and find the optimal one among them with respect to hardware complexity and operating frequency The Viterbi decoder with a optimal hardware architecture is designed and verified by using Verilog HDL, and synthesized into gate-level circuits with TSMC 0.13um library. In the synthesis results, we find that the Viterbi decoder contains about 280K gates and works properly at the speed required in MB-OFDM systems.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.969-976
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• 2019

A lightweight artificial intelligence hardware has made great strides in many application areas. In general, a lightweight artificial intelligence system consist of lightweight artificial intelligence engine and preprocessor including feature selection, generation, extraction, and normalization. In order to achieve optimal performance in broad range of applications, lightweight artificial intelligence system needs to choose a good preprocessing function and set their respective hyper-parameters. This paper proposes a unified framework for a lightweight artificial intelligence system and utilization method for finding models with optimal performance to use on a given dataset. The proposed unified framework can easily generate a model combined with preprocessing functions and lightweight artificial intelligence engine. In performance evaluation using handwritten image dataset and fall detection dataset measured with inertial sensor, the proposed unified framework showed building optimal artificial intelligence models with over 90% test accuracy.