• Journal of Broadcast Engineering
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• v.3 no.1
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• pp.85-92
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• 1998

The block matching algorithm is the most popular motion estimation method in image sequence coding. In this paper, we propose a VLSI architecture. for implementing a recently proposed fast bolck matching algorith, which uses spatial correlation of motion vectors and hierarchical searching scheme. The proposed architecture consists of a basic searching unit based on a systolic array and two shift register arrays. And it covers a search range of -32~ +31. By using the basic searching unit repeatedly, it reduces the number of gatyes for implementation. For basic searching unit implementation, a proper systolic array can be selected among various conventional ones by trading-off between speed and hardware cost. In this paper, a structure is selected as the basic searching unit so that the hardware cost can be minimized. The proposed overall architecture is fast enough for low bit-rate applications (frame size of $352{\times}288$, 3Oframes/sec) and can be implemented by less than 20,000 gates. Moreover, by simply modifying the basic searching unit, the architecture can be used for the higher bit-rate application of the frame size of $720{\times}480$ and 30 frames/sec.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.225-228
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• 2011

동영상을 고효율로 압축할 수 있는 중요한 기술 중의 하나가 움직임 추정 기술이다. 움직임 추정 기술에서 가장 널리 사용되는 탐색 방식과 정합오차를 판단하는 기준은 각각 전역 탐색(FS: Full Search)알고리듬과 Sum of Absolute Differences(SAD)이다. 하지만, FS와 SAD를 사용한 움직임 추정기술은 인코더 전체 계산량의 50%이상을 차지하게 된다. 무선 통신 및 인터넷 환경에서 사용되는 응용프로그램에 대해서는 많은 계산량이 실시간 전송을 어렵게 만든다. 이러한 이유로, 동영상 압축 기술에서 계산량을 줄이는 방법이 중요하게 되었다. 그 결과로, SAD대신 다른 정합 오차 기준을 사용하여 움직임 추정기술의 계산량을 줄이는 알고리듬들이 제안되었다. 본 논문에서는 계산량을 줄이면서 하드웨어 구현 시 많은 이점을 가진 1비트 변환 (One-bit Transform, 1BT)알고리듬과 1비트 변환의 성능을 향상시킨 제한된 1비트 변환(Constrained one-bit transform, C-1BT)을 소개하고 C-1BT방법에 있어서 기존 방식의 빠른 인코딩속도를 유지하면서 PSNR을 증가시키는 알고리듬을 제안한다. 제안하는 알고리듬에서는 기존 C-1BT에서 고정해서 사용한 파라미터 D값을 대신에 현재블록과 동일한 위치에 있는 참조영역의 블록과 그 주변블록의 움직임벡터 정보를 이용해서 블록의 움직임 정도를 판단하고, 블록단위로 D값을 적응적으로 결정한다. 실험결과는 제안하는 알고리듬이 기존의 알고리듬과 비교하여 평균 0.11dB PSNR 증가를 보여 준다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2012.11a
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• pp.129-131
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• 2012

본 논문은 2비트 변환 (two-bit transform : 2BT) 알고리즘의 탐색 범위를 적응적으로 조정하는 알고리즘을 제안하였다. 2BT는 정합 오차 기준으로 SAD (sum of absolute differences)를 사용하지 않고 Number of Non-Matching Points (NNMP)를 사용하여 속도를 향상시키고, 하드웨어 구현을 용이하게 했다. 그러나 움직임 예측 시 기존의 방법인 전역 탐색 (FS : Full Search) 알고리즘을 사용하여 방대한 연산량을 요구한다. 이 점을 개선하기 위해 이 논문에서는 2BT의 탐색 범위를 매 블록마다 적응적으로 조정하면서 알고리즘의 계산량을 줄이고 속도를 향상시키는 알고리즘을 제안하였다. 기존의 2BT와 제안하는 알고리즘을 비교한 실험결과는 PSNR이 거의 동일하나 복잡도 측면에서 제안하는 알고리즘이 훨씬 우수한 성능을 보여준다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1049-1058
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• 2009

After the efficiency of H.264 video compression has been announced, it replaced MPEG-2 standard in several applications. So transcoding methods of MPEG-2 to H.264 have been studying because there are variety devices and contents followed by MPEG-2. Although H.264 supported various service such as IPTV, DMB, digital broadcasting etc, but users using MPEG-2 devices cannot accessible to them. This paper propose H.264 to MPEG-2 transcoding for users of MPEG-2 devices without displacement H.264. The proposed method predicted a motion vector for MPEG-2 encoder after it extracted from motion vectors of variable blocks in H.264 to improve processing time. Also it predicted a optimal motion vector using modified boundary matching algorithm after grasped a special character for boundary and background of object. The experimental results from proposed method show a considerable reduction in processing time, as much as 65% averagely, with a small objective quality reduction in PSNR.

• Journal of KIISE:Software and Applications
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• v.35 no.1
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• pp.1-11
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• 2008

This paper detected the characteristics of motion vector to support efficient content -based video search of video. Traditionally, the present frame of a video was divided into blocks of equal size and BMA (block matching algorithm) was used, which predicts the motion of each block in the reference frame on the time axis. However, BMA has several restrictions and vectors obtained by BMA are sometimes different from actual motions. To solve this problem, the foil search method was applied but this method is disadvantageous in that it has to make a large volume of calculation. Thus, as an alternative, the present study extracted the Spatio-Temporal characteristics of Motion Vector Spatio-Temporal Correlations (MVSTC). As a result, we could predict motion vectors more accurately using the motion vectors of neighboring blocks. However, because there are multiple reference block vectors, such additional information should be sent to the receiving end. Thus, we need to consider how to predict the motion characteristics of each block and how to define the appropriate scope of search. Based on the proposed algorithm, we examined motion prediction techniques for motion compensation and presented results of applying the techniques.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.69-77
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• 2002

Sine digital signal processing for motion pictures requires huge amount of data computation to store, manipulate and transmit, more effective data compression is necessary. Therefore, the ITU-T recommended H.26x as data compression standards for digital motion pictures. The data compression method that eliminates time redundancies by motion estimation using relationship between picture frames has been widely used. Most video conding systems employ block matching algorithm for the motion estimation and compensation, and the algorithm is based on the minimun value of cast functions. Therefore, fast search algorithm rather than full search algorithm is more effective in real time low data rates encodings such as H.26x. In this paper, motion estimation employing the Nearest-Neighbors algorithm is designed to reduce search time using FPGA, coded in VHDL, and simulated and verified using Xilink Foundation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.