• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.10 s.340
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• pp.39-46
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• 2005

A DC-DC converter with digital controller is realized. the digital controller has several advantages such as robustness, fast design time, and high flexibility. however, since the DC-DC output voltage is analog, an analog-to-digital conversion scheme is always essential in all digital controllers. A simple and efficient delta-sigma modulator is used as a conversion scheme in out implementation. The measurement results show good voltage regulation

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.331-334
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• 2004

본 논문에서는 클록의 duty ratio가 변하였을 때, 그 클록의 duty ratio를 $50\%$의 duty ratio로 만들어 주는 Pulse Width Control Loop Circuit을 설계하였다. 기존의 논문에서는 duty ratio를 변화시키기 위해 각 duty ratio 마다 알맞은 제어 전압을 공급해하는 문제점이 있었다. 본 논문은 제어 전압이 변하지 않고 일정한 전압으로도 duty ratio를 변화시킬 수 있게 하여, 제어 전압 변화에 대한 문제점을 해결하였다. 설계, 시뮬레이션 결과 기존의 논문보다 간단해진 회로 구성으로 더욱 높은 주파수에서 동작하였다. 그리고 settling 시간도 기존의 논문의 l00ns 이상에서 5ns로 줄어듦을 확인할 수 있었다. 본 논문은 3.3V의 공급 전압에서 $0.35{\mu}m$ CMOS공정을 이용하여 설계하였고 동작 주파수는 500MHz-2GHz였고, settling 시간은 10n이하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.10-21
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• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.561-572
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• 2001

Since energy consumption of CMOS circuits has a quadratic dependency on the supply voltage, lowering the supply voltage is the most effective way of reducing energy consumption. We propose an intra-task voltage scheduling algorithm for low-energy hard real-time applications. Based on a static timing analysis technique, the proposed algorithm controls the supply voltage within an individual task boundary. By fully exploiting all the slack times, as scheduled program by the proposed algorithm always complete its execution near the deadline, thus achieving a high energy reduction ratio. In order to validate the effectiveness of the proposed algorithm, we built a software tool that automatically converts a DVS-unaware program into an equivalent low-energy program. Experimental results show that the low-energy version of an MPEG-4 encoder/decoder (converted by the software tool) consumes less than 7~25% of the original program running on a fixed-voltage system with a power-down mode.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.8-11
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• 2003

본 연구는 AC서보 모터의 벡터 제어를 구현하는데 있어 디지털 제어에 의한 시간 지연 및 Af) 변환기, QEP(Quadrature Encoder Pulse Circuit)등 주변 소자의 시간 지연에 의한 노이즈를 최소화하지 위하여 고성능 저 전압형 DSP인 TMX320F2812를 사용하였다. TMX320F2812는 150MIPS의 빠른 연산 속도와 12비트의 AD 컨버터, QEP회로는 물론 공간 전압 벡터 PWM을 발생시킬 수 있는 기능을 가진 모터 제어용 원친 DSP이다. 이와 같이 주변 회로들을 내장한 고성능 DSP의 사용은 모터 제어부의 하드웨어적인 구성을 간소화 시키고 이로 인한 비용 절감을 얻을 수 있다. 또한 전류 샘플을 위한 필터 부분을 디지털 필터화 하여 전류 샘플링 노이즈를 제거하였고, 옵셋 전압을 이용한 SVPWM을 구현하여 연산 시간을 대폭 단축 하였다. TMX320F2812의 단점인 고정 소수점 연산에 대해서는 각 변수에 대한 스케일링을 통해 유효 자리를 확보하였다.

• Journal of IKEEE
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• v.13 no.4
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• pp.9-14
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• 2009

This paper describes measurement of an on-ship power supply noise in mixed-signal integrated circuits. To measure the on-chip power supply noise, we can check the effects of analog circuits and compensate it. This circuit consists of two independent measurement channels, each consisting of a sample and hold circuit and a frequency to digital converter which has a buffer and voltage controlled oscillator(VCO). The time-based voltage information and frequency-based power spectrum density(PSD) can be achieved by a simple analog to digital conversion scheme. The buffer works like a unit-gain buffer with a wide bandwidth and VCO has a high gain to improve resolution. This circuit was fabricated in a 0.18um CMOS technology and has 2.06mV/count. The noise measurement circuit consumes 15mW and occupies $0.768mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.95-103
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• 2007

Dynamic voltage scaling (DVS) is a well-known and effective power management technique. While there has been research on slack distribution, voltage allocation and other aspects of DVS, its effects on non-voltage-scalable devices has hardly been considered. A DC-DC converter plays an important role in voltage generation and regulation in most embedded systems, and is an essential component in DVS-enabled systems that scale supply voltage dynamically. We introduce a power consumption model of DC-DC converters and analyze the energy consumption of the system including the DC-DC converter. We propose an energy-optimal off-line DVS scheduling algorithm for systems with DC-DC converters, and show experimentally that our algorithm outperforms existing DVS algorithms in terms of energy consumption.