• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2176-2182
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• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.85-93
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• 2005

Interior permanent magnet synchronous motor(IPMSM) has become a popular choice in electric vehicle applications, due to their excellent power to weight ratio. The paper is posed maximum torque control of IPMSM for high speed drive. The control method is applicable over the entire speed range and considered the limits of the inverter's current and voltage rated value. For each control mode, a condition that determines the optimal d-axis current $i_d$ for maximum torque operation is derived. The proposed control algorithm is applied to IPMSM drive system for high speed drive, the operating characteristics controlled by maximum torque control are examined in detail by experiment.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.264-266
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• 2012

엘리베이터 제동 시 발생하는 인버터 회생 전류는 많은 고조파를 포함하고 있다. 기존의 회생용 인버터는 계통 측 필터로 L필터가 많이 사용되어 왔으나, 고조파를 저감하기 위해서 매우 큰 L값을 요구한다. 하지만 엘리베이터 회생용 인버터는 기설치된 DC Link 과전압 방지 방전회로가 동작되기 전에 회생을 실시하여야 하므로, 상대적으로 낮은 전압에서 회생되어야 하므로 큰 임피던스를 갖는 L필터를 사용하기 어렵다. 본 논문에서는 엘리베이터 회생용 인버터의 리플저감용 LCL 필터와 최근 제안된 LLCL 필터의 성능을 비교 분석하고 모의해석과 실험을 통해 그 타당성을 입증 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.53-60
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• 2005

This work proposes a 10b 100 MS/s $1.4\;mm^2$ CMOS ADC for low-power multimedia applications. The proposed two-step pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The wide-band SHA employs a gate-bootstrapping circuit to handle both single-ended and differential inputs with 1.2 Vp-p at 10b accuracy while the second-stage flash ADC employs open-loop offset sampling techniques to achieve 6b resolution. A 3-D fully symmetrical layout reduces the capacitor and device mismatch of the first-stage MDAC. The low-noise references are integrated on chip with optional off-chip voltage references. The prototype 10b ADC implemented in a 0.18 um CMOS shows the maximum measured DNL and INL of 0.59 LSB and 0.77 LSB, respectively. The ADC demonstrates the SNDR of 54 dB, the SFDR of 62 dB, and the power dissipation of 56 mW at 100 MS/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.65-73
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• 2006

This work presents a 14b 200KS/s $0.87mm^2$ 1.2mW 0.18um CMOS algorithmic A/D converter (ADC) for intelligent sensors control systems, battery-powered system applications simultaneously requiring high resolution, low power, and small area. The proposed algorithmic ADC not using a conventional sample-and-hold amplifier employs efficient switched-bias power-reduction techniques in analog circuits, a clock selective sampling-capacitor switching in the multiplying D/A converter, and ultra low-power on-chip current and voltage references to optimize sampling rate, resolution, power consumption, and chip area. The prototype ADC implemented in a 0.18um 1P6M CMOS process shows a measured DNL and INL of maximum 0.98LSB and 15.72LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 54dB and 69dB, respectively, and a power consumption of 1.2mW at 200KS/s and 1.8V. The occupied active die area is $0.87mm^2$.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.6
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• pp.504-511
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• 2003

In this paper, inverter type neon power supply using a piezoelectric transformer is fabricated and its characteristic is investigated. Developed neon power supply is composed of basic circuit and blocks, such as rectifier part, frequency oscillation part and piezoelectric transformer and resonant half bridge inverters. In this paper for complement the low power limitation, piezoelectric transformer at parallel connected driving by inverter is studied for noon tubes system of high power. When piezoelectric transformer is connected with parallel, LC filter connection method with parallel and selection of inductance L and capacitor C of primary side is suggested for reduce unbalanced current at the terminal of each transformer. Piezoelectric transformers use piezoelectric ceramic devices. Thus it is wireless therefore it has high power density, high Isolation level, low loss, more light, and miniaturization. In addition, high voltage transfer ratio is expected because there is no leakage inductance. Also, it has economic merit that the electrical loss Is low because structure is simple, small and tighter weight.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.3
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• pp.259-268
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• 2014

In this paper, we suggest a method of extracting circuit parameters of the insulating transformer using S-parameter measurement, especially in high frequency range. At 60 Hz, conventionally, no load test and short circuit test are used to extract the circuit parameters. In this paper S-parameters measured from VNA(Vector Network Analyzer) were used to extract the transformer parameters using data fitting method (optimization). The S-parameters from the equivalent circuit using the extracted parameters showed good agreement with those from measurement. Furthermore, the transformer secondary voltages from the equivalent circuit model also coincide quite exactly to the measured secondary voltages in sinusoidal forms. Finally we assert that the proposed method to extract the parameters for the insulating transformer using S-parameter is valid especially in high frequency.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.2
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• pp.67-74
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• 2002

The paper deals with a fully assumed strain soild element that can be used for modeling of thin sensors and actuators. To solve fully coupled field problems, the eledtric potential is regarded as a nodal degree of freedom in addition to three translations in an eighteen node assumed strain soild element. Therefore, the induced electric potential can be calculated for a prescribed load and the actuation displacement can be computed for an input voltage. Since the assumed strain solid element can alleviate locking. A finite element code is developed based on the formulation and typical numerical examples are solved for code validation. Using the code, we have conducted parametric study for THUNDER actuator. It is found that a particular combination of materials for layer curvature of THUNDER improves the actuation displacement.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.47-47
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• 2010

지구온난화의 심화로 사회적으로 환경의 중요성에 대한 인식이 확산되면서 $CO_2$ 배기가스 및 연비와 직결되어 있는 자동차 중량 절감의 중요성이 강조됨에 따라 차체 경량화 기술은 환경 친화적인 자동차 개발의 핵심기술로 연구되고 있다. 그러나 충돌보호 장치 및 편의장치의 증가로 차체 중량은 지속적으로 증가하고 있어 차체 중량을 혁신적으로 절감할 수 있는 초경량 차체기술이 요구된다. 차체 경량화 방법으로 기존 강재를 알루미늄재로 대체하는 방안이 연구되고 있으며, 일부 해외 고급 차종에서 알루미늄재를 이용한 스페이스 프레임 및 부품 개발을 검토 적용 중이다. 그러나 알루미늄 단일재 사용은 안전성등에서 요구 성능을 만족시키기 어렵기 때문에 강재와 알루미늄재의 적절한 사용이 필요하다. 이를 위하여 강재와 알루미늄간 이종접합부가 발생하며 이를 위한 적정 공정 개발이 필요하다. 전자기 펄스 용접(MPW)은 고상접합의 한 종류로서 고전류를 순간적으로 방전하여 발생된 고에너지를 통하여 접합이 이루어진다. 이러한 고에너지는 외부재의 전 자기적 성질에 의하여 에너지량이 결정되므로 외부재의 전도도(conductivity)는 매우 중요하며 이러한 이유로 Aluminum 1xxx계 중심의 전자기 펄스 용접 공정이 연구되었다. 그러나 자동차 스페이스 프레임 및 드라이브 샤프트등과 같은 부품에 알루미늄재를 적용하기 위해서는 일정 강도를 확보할 수 있는 6xxx계의 관련 연구가 필요하다. 따라서 본 연구에서는 고품질의 접합부 확보를 위한 1xxx계와 6xxx의 최적의 공정변수(충전전압, 외부재와 내부재 사이의 간격, 외부재 두께)를 도출하였다. 이를 위하여 전자기 펄스 용접 장치는 한국생산기술연구원과 웰메이트(주)에서 공동으로 개발한 $120{\mu}F$의 캐패시터 6개로 구성된 'W-MPW36'을 사용하였으며 접합 후 누수시험을 통하여 접합부의 품질을 검토하였다.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.