• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.63-67
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• 2010

The organic solar cells with Glass/ITO/PEDOT:PSS/P3HT:PCBM/Al structure were fabricated using regioregular poly (3-hexylthiophene) (P3HT) polymer:(6,6)- phenyl $C_{61}$-butyric acid methyl ester (PCBM) fullerene polymer as the bulk hetero-junction layer. The P3HT and PCBM as the electron donor and acceptor materials were spin casted on the indium tin oxide (ITO) coated glass substrates. The optimum mixing concentration ratio of photovoltaic layer was found to be P3HT:PCBM = 4:4 in wt%, indicating that the short circuit current density ($J_{SC}$), open circuit voltage ($V_{OC}$), fill factor (FF) and power conversion efficiency (PCE) values were about 4.7 $mA/cm^2$, 0.48 V, 43.1% and 0.97%, respectively. To investigate the effects of the post annealing treatment, as prepared organic solar cells were post annealed at the treatment time range from 5min to 20min at $150^{\circ}C$. $J_{SC}$ and $V_{OC}$ increased with increasing the post annealing time from 5min to 15min, which may be originated from the improvement of the light absorption coefficient of P3HT and improved ohmic contact between photo voltaic layer and Al electrode. The maximum $J_{SC},\;V_{OC}$, FF and PCE values of organic solar cell, which was post annealed for 15min at $150^{\circ}C$, were found to be about 7.8 $mA/cm^2$, 0.55 V, 47% and 2.0%, respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.51-55
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• 2006

The green emitting high performance OLEDs using the $Alq_3$-C545T fluorescent system have been fabricated and characterized. In the device fabrication, 2-TNATA [4,4',4'-tris(2-naphthylphenyl-phenylamino)-triphenylamine] as a hole injection material and NPB [N,N'-bis(1-naphthyl)-N,N'-diphenyl-1,1'-biphenyl-4,4'-diamine] as a hole transport material were deposited on the ITO(indium thin oxide)/glass substrate by vacuum evaporation. And then, green color emission layer was deposited using $Alq_3$ as a host material and C-545T[10-(2-benzothiazolyl)-1,1,7,7- tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-[1]/benzopyrano[6,7,8-ij]-quinolizin-11-one] as a dopant. Finally, small molecule OLEDs with structure of ITO/2-TNATA/NPB/$Alq_3$:C545T/$Alq_3$/LiF/Al were obtained by in-situ deposition of $Alq_3$, LiF and Al as the electron transport material, electron injection material and cathode, respectively. Green OLEDs fabricated in our experiments showed the color coordinate of CIE(0.29, 0.65) and the maximum power efficiency of 7.3 lm/W at 12 V with the peak emission wavelength of 521 nm.

• Applied Chemistry for Engineering
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• v.31 no.3
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• pp.291-298
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• 2020

ZITO/Ag/ZITO multilayer transparent electrodes at room temperature on glass substrates were prepared using RF/DC magnetron sputtering. Transparent conductive films with a sheet resistance of 9.4 Ω/㎡ and a transmittance of 83.2% at 550 nm were obtained for the multilayer structure comprising ZITO/Ag/ZITO (100/8/42 nm). The sheet resistance and transmittance of ZITO/Ag/ZITO multilayer films meant that they would be highly applicable for use in polymer-dispersed liquid crystal (PDLC)-based smart windows due to the ability to effectively block infrared rays (heat rays) and thereby act as an energy-saving smart glass. Effects of the thickness of the PDLC layer and the intensity of ultraviolet light (UV) on electro-optical properties, photopolymerization kinetics, and morphologies of difunctional urethane acrylate-based PDLC systems were investigated using new transparent conducting electrodes. A PDLC cell photo-cured using UV at an intensity of 2.0 mW/c㎡ with a 15 ㎛-thick PDLC layer showed outstanding off-state opacity, good on-state transmittance, and favorable driving voltage. Also, the PDLC-based smart window optimized in this study formed liquid crystal droplets with a favorable microstructure, having an average size range of 2~5 ㎛ for scattering light efficiently, which could contribute to its superior final performance.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.49-49
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• 2010

용접은 산업계의 기계 조립 및 접합을 위한 공정의 주요한 작업으로 조선, 중공업, 건설 등 산업현장에서 사람에 의한 수동적인 작업으로 대부분 수행된다. 이러한 용접 작업을 수행하는 용접 기술자는 산업 현장 훈련원과 직업 교육 학교에서 양성되지만 용접 훈련 과정은 실습 초보자에게 위험하고, 장시간 교육하기에 어려울 뿐 아니라 재료 낭비, 의사 소통의 한계, 즉석 결과 평가의 한계, 공간부족 등 다양한 문제가 있다. 그러므로, 안전하고 반복적인 실습 환경 제공하고 장시간 및 다수 교육참여 지원 등이 가능한 시스템을 구축하여 숙련된 우수 인력 조기 확보와 훈련 비용을 절감할 필요가 있다. 본 논문에서는 실제와 동일한 상호작용을 제공할 뿐만 아니라 고품질로 훈련 환경을 가시화하여 용접 상황을 동일하게 모사하는 가상 현실 기반 용접 훈련 시뮬레이터를 제시한다. 이 시스템은 용접의 형상과 환경의 고품질 가시화, 경험 DB를 통한 용접의 비드 형상 데이터 획득, 용접 토치를 이용하는 사용자 상호작용, 용접 훈련 결과 평가 및 최적 작업 가이드, 용접 콘텐츠 저작, 다양한 용접 훈련을 가시화하는 하드웨어 플랫폼으로 구성된다. 고품질 가상 용접 가시화는 경험 DB 기반 비드 형상 데이터와 신경회로망을 이용한 비드 형상 예측을 통해 실시간 비드 표현이 이루어지며 쉐이더 기반 고품질 모재 및 비드 표현, 아크 불꽃 효과 표현을 포함한다. 사용자 상호작용은 현장 작업 도구와 일치된 토치 인터페이스와 위치추적을 이용하여 토치의 작업각, 진행각, 속도, 거리 등을 반영할 수 있으며 진동과 소리 등 용접 훈련의 사실적 상호작용도 재현하였다. 용접 훈련 평가 및 최적 작업 가이드는 훈련자의 용접속도, 거리, 각도 등의 사용자 작업 결과를 그래픽으로 표현하고, 애니메이션을 통한 훈련 자세를 추후 분석할 수 있도록 하였고, 가상토치, 기준선, 수치계기 등을 이용한 최적 작업 훈련 가이드 제시하였다. 훈련 콘텐츠 저작은 메뉴UI 기반으로 용접의 전류, 전압 등의 조건과 상황을 선택하도록 제시하였고, 하드웨어 플랫폼은 워크벤치형 입체 디스플레이 방식으로 용접 환경을 가시화하였고, 위, 정면, 아래보기 등 다양한 용접 자세 변경을 지원 할 수 있도록 구축하였다. 이러한 가상현실 기반 훈련 시뮬레이터는 아크열 발생에 따른 장시간 훈련의 어려움을 극복할 수 있고, 다양한 실습 환경을 바꾸어 가며 반복적인 훈련이 가능하고, 실 재료를 사용하지 않아 재료의 낭비를 줄일 수 있는 환경 친화적인 안전하고 효율적인 훈련 실습 환경을 제공할 수 있다.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.148-148
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• 1999

다이아몬드에 버금가는 높은 경도뿐만 아니라 높은 화학적 안정성 및 열전도성 등 우수한 물리화학적 특성을 가진 입방정 질화붕소(cubic Boron Nitride)는 마찰.마모, 전자, 광학 등의 여러 분야에서의 산업적 응용이 크게 기대되는 자료이다. 특히 탄화물형성원소에 대해 안정하여 철계금속의 가공을 위한 공구재료로의 응용 또한 기대되는 재료이다. 특히 탄화물형성원소에 대해 안정하여 철계금속의 가공을 위한 공구재료로의 응용 또한 크게 기대된다. 이 때문에 각종의 PVD, CVD 공정을 이용하여 c-BN 박막의 합성에 대한 연구가 광범위하게 진행되어 많은 성공사례들이 보고되고 있다. 그러나 이러한 c-BN 박막의 유용성에도 불구하고 아직 실제적인 응용이 이루어지지 못한 것은 증착직후 급격한 박리현상을 보이는 c-BN 박막의 밀착력문제때문이다. 본 연구에서는 평행자기장을 부가한 ME-ARE(Magnetically Enhanced Activated Reactive Evaporation)법을 이용하여 c-BN 박막을 합성하고, 합성된 c-BN 박막의 밀착력에 미치는 공정인자의 영향을 규명하여, 급격한 박리현상을 보이는 c-BN 박막의 밀착력 향상을 위한 최적 공정을 도출하고자 하였다. BN 박막 합성은 전자총에 의해 증발된 보론과 (질소+아르곤) 플라즈마의 활성화반응증착(activated reactive evaporation)에 의해 이루어졌다. 기존의 ARE장치와 달리 열음극(hot cathode)과 양극(anode)사이에 평행자기장을 부여하여 플라즈마를 증대시켜 반응효율을 높혔다. 합성실험용 모재로는 p-type으로 도핑된 (100) Si웨이퍼를 30$\times$40 mm크기로 절단 후, 100%로 희석된 완충불산용액에 10분간 침적하여 표면의 산화층을 제거한후 사용하였다. c-BN 박막을 얻기 위한 주요공정변수는 기판바이어스 전압, discharge 전류, Ar/N가스유량비이었다. 증착공정 인자들을 변화시켜 다양한 조건에서 c-BN 박막의 합성하여 밀착력 변화를 조사하였다. 합성된 박막의 결정성 분석을 FTIR을 이용하였으며, Bn 박막의 상 및 미세구조관찰을 위해 투과전자현미경(TEM;Philips EM400T) 분석을 병행하였고, 박막의 기계적 물성 평가를 위해 미소경도를 측정하였다. 증착된 c-BN 박막은 3~10 GPa의 큰 잔류응력으로 인해 증착직후 급격한 박리현상을 보였다. 이의 개선을 위해 증착중 기판바이어스 제어 및 후열처리를 통해 밀착력을 수~수백배 향상시킬 수 있었다. c-BN 박막의 합성을 위해서는 증착중인 박막표면으로 큰 에너지를 갖는 이온의 충돌이 필요하기 때문에 기판 바이어스가 요구되는데, c-BN의 합성단계를 핵생성 단계와 성장 단계로 구분하여 인가한 기판바이어스를 달리하였다. 이 결과 그림 1에서 나타낸 것처럼 c-BN 박막의 핵생성에 필요한 기판바이어스의 50% 정도만을 인가하였을 때 잔류응력은 크게 경감되었으며, 밀착력이 크게 향상되었다.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.59-64
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• 2008

In this paper, white polymer light emitting diodes(WPLEDs) were fabricated and investigated the electrical and optical properties for the prepared devices. ITO(indium tin oxide) and PEDOT:PSS [poly(3,4-ethylenedioxythiophene):poly(styrene sulfolnate)] as anode and hole injection materials, PFO [poly(9,9-dioctylfluorene)] and MEH-PPV [poly(2-methoxy-5(2-ethylhe xoxy)-1,4-phenylenevinyle)] were used as the light emitting host and guest materials, respectively. The LiF(lithium flouride) and Al(aluminum) were used electron injection materials and cathode materials. Finally, the WPLED with structure of ITO/PEDOT:PSS/PFO:MEH-PPV/LiF/Al was fabricated. The prepared WPLED showed white emission with CIE coordinates of (x=0.36, y=0.35) at the applied voltage of 9V. The maximum current density and luminance were about $740mA/cm^2\;and\;900cd/m^2$ at 13V, respectively. And the maximum current efficiency was 0.37 cd/A at $200cd/m^2$ in luminance.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.6
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• pp.275-281
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• 2017

AlN is a promising material for wide band gap and high-frequency electronics device due to its wide bandgap and high thermal conductivity. AlN has advantages as materials for power semiconductors with a larger breakdown field, and a smaller specific on-resistance at high voltage. The growth of a p-type AlN epilayer with high conductivity is important for a manufacturing an AlN-based applications. In this paper, Mg doped AlN epilayers were grown by a mixed-source HVPE. Al and Mg mixture were used as source materials for the growth of Mg-doped AlN epilayers. Mg concentration in the AlN was controlled by modulating the quantity of Mg source in the mixed-source. Surface morphology and crystalline structure of AlN epilayers with different Mg concentrations were characterized by FE-SEM and HR-XRD. XPS spectra of the Mg-doped AlN epilayers demonstrated that Mg was doped successfully into the AlN epilayer by the mixed-source HVPE.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.