• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.634-638
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• 2015

Phase currents should be measured in real time for vector control of a 2-phase induction motor. Generally, the phase currents of the motor are measured using two Hall current sensors installed at the output terminal of an inverter. Unfortunately, Hall current sensors are expensive and uneconomical because a vector-controlled inverter for 2-phase induction motor is mainly used in low-power and low-price applications. This paper proposes a low-cost current measurement method using two shunt resistors instead of expensive Hall current sensors. The proposed method can measure the phase currents under all operating conditions of the motor. This method was applied to an experimental vector-controlled inverter for 2-phase induction motor of 220[V]/360[W] and was verified through computer simulations and experimentation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.11
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• pp.6804-6809
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• 2014

This paper presents a bandpass filter using a current differencing transconductance amplifier (CDTA)s for application to low-voltage and low-power analog signal processing systems. The presented filter employs grounding and floating active inductors, which are composed of two or three CDTAs, and is capable of realizing all the standard functions of the filter without requiring any component matching criteria or extra active components. The HSPICE simulation result of the designed active bandpass filter showed that it had a 10MHz center frequency with -2.5dB attenuated bandwidth from 9.5 MHz to 10.5 MHz, and -50dB from 8 MHz to 17 MHz.

• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.556-561
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• 2016

This paper describes implementation of a 13.56 MHz, 5 kW RF high power generator for ISM band applications. This RF generator consists of four LDMOS modules of 1.25kW class-AB push-pull power amplifier with drive amplifier and its outputs are combined by using Wilkinson type transmission-line transformers. Its generator has a high efficiency and output power better than linearity. In order to discharge power transistor heats, we used on water cooled copper plate. Also, these have a composite circuit of combiner and low-pass filter and safety circuit to detector over and reflected power. The RF generator has achieved a efficiency of 79 % at 5.33 kW of saturated power level experimentally.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2226-2234
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• 2016

Orthogonal Frequency Division Multiplexing (OFDM) technique uses multiple sub-carriers for the data transmission. Therefore, Inter Carrier Interference(ICI) is generated because of nonlinear high power amplifier and carrier frequency offset. Wireless OFDM transmission over Doppler fading channels also causes ICI. In OFDMA(Orthogonal Frequency Division Multiplexing Access), multiple sub-carriers are allocated to each user. Therefore, inter carrier interference causes interference to other users. I evaluate the BER performance of OFDMA systems in frequency selective fading channel, considering Multi-User Interference (MUI) owing to the carrier frequency offset, the nonlinear high power amplifier, and the Doppler fading. In the uplink OFDMA, multi-user interference introduces larger BER degradation than in the downlink. I explain the reason and obtain the required characteristics of the nonlinear amplifier and the value of frequency offset for good BER performance. And I also analyze the BER degradation upon Doppler fading channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.194-200
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• 2006

A 26.4 GHz phase locked oscillator(PLO) for communication satellite transponder is developed. The PLO consists of fundamental frequency generation module(FFGM) and frequency multiplication part(FMP). The signal of 26.4 GHz is generated through frequency tripling process of 8.8 GHz fundamental frequency. Phase locking technique using sampling phase detector(SPD) is adopted to design the FFGM. The MMIC tripler and amplifier are also designed for the reduction of the size and mass of FMP. The phase noise characteristics are exhibited as -96 dBc/Hz at 10 tHz offset frequency and -105 dBc/Hz at 100 kHz offset frequency, respectively, with the output power over 11 dBm. All performance parameters are complied with the design requirements.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.54-61
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• 1999

This paper describes the design of a 4-Mbps wireless infrared data transceiver chip. The receiver consits of the analog front-end, clock recovery and frame generator, and demodulator. The transmitter consists of the demodulator and LED driver. The versatile analog front- end consisting of multiple amplifiers makes it possible for the chip to be applied to various infrared environments by compensating DC and offset signal components. A 4PPM (pulse position modulation) scheme is used for data transfer in order to meet the IrDA standards. The chip was fabricated in a $0.8-{\mu}m$ 2-poly, 2-metal CMOS technology and dissipates 122mW for ${\pm}2.5V$ supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.967-973
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• 2003

This paper presents a new predistortion method which injects the 2nd low-frequency intermodulation signal of RF signals into the input bias line of the amplifier. New 2nd intermodulation signal extraction circuit is also proposed. We have shown that this method can suppress the 3rd IM apparently and sometimes do the 5th IM, through mathematical analysis, then confirmed it with simulation and verified it on the desk test. When the input signal CDMA IS-95 lFA is applied, measured ACPR improvements are 25 dBc, 22.5 dBc, and 6 dBc at 0.885 MHz, l.25 MHz and 2.25 MHz offset respectively. Also, when applying the CDMA IS-95 3FA, the measured ACPR improvement is 20 dBc at 0.885 MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.1
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• pp.79-87
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• 2013

A new modulation technique - correlative encoded FSK (CEFSK) - for use in power and bandwidth limited digital communication system is proposed. CEFSK is free of ISI and generates output signals which have a smooth and continuous phase transition and a reduced envelope fluctuation by keeping correlation between amplitude and phases of two subsequent symbols. In comparison to conventional one-bit differential detected (1DD) GFSK, the performance of the 1DD-CEFSK in a non-linearly amplified (NLA) channel impaired by additive white Gaussian noise (AWGN), ISI and IM, is analyzed via computer simulation. The simulation result shows that, in an NLA single-channel, 1DD-CEFSK provides a signal-to-noise ratio (SNR) advantage of up to 1.2dB and 0.8dB at BER of $1{\times}10^{-4}$ when input back-off (IBO) of HPA is -1.0dB and -3.0dB, respectively. For the same channel environment with multi-channel, 1DD-CEFSK outperforms 1DD-GFSK by 1.1dB in SNR, regardless of the value of IBO.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.15-20
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• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.