• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.11-18
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• 2012

In this paper, we propose a novel equal-gain differential precoding scheme utilizing temporal correlation of channels. The conventional differential precoding schemes only quantize a part of channel space not the whole channel space, so that it virtually increases codebook size which enhances the system capacity. But the conventional differential schemes increase peak-to-average power ratio (PAPR) without preserving equal-gain transmission. This paper proposes the design method of equal-gain differential precoding scheme and analyzes the performances of the proposed equal-gain precoding scheme. Monte-Carlo simulations verify that the proposed scheme has an advantage of 1dB to obtain the same system capacity with the same amount of feedback information compared with the conventional LTE schemes, with showing very low PAPR property.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.71-80
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• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.330-331
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• 2005

본 논문에서는 카메라폰용 광학중(Optical zooming) 과 자동초점조절장치 (Auto Focusing, AF)에 쓰일 초음파모터를 제작하였다. 초음파모터의제작 및 시뮬레이션은 유한요소해석 프로그램인 ATILA 5.2.1 (Magsoft co.)를 사용하여 디자인설계에 따른 구동특성을 고찰하였고 제작된 초음파모터는 한쪽 면이 없는 사작형의 탄성체를 제작하였으며 탄성체의 양쪽 다리에 각각 압전체를 부착하였다. 또한 압전세라믹의 조성은 $0.9Pb(Zr_{0.51}Ti_{0.49})O_3-0.1Pb(Mn_{1/3}Nb_{1/3}Sb_{1/3})O_3$의 조성으로 설계하였고 시편의 제조는 7-layer로 적층하였다. 제작된 압전세라믹의 치수는 6*2*0.35$mm^3$(길이*폭*두께)로 제작하였다 또한 탄성체의 외형치수는 10*10*2$mm^3$로 제작하였으며 두께를 각각 0.3[mm], 0.5[mm], 0.8[mm]으로 변화시키며 제작하였다. 두께가 0.8[mm]인경우 공진주파수는 60.5[kHz]를 나타내었으며 초음파모터의 압전세라믹에 인가전압이 증가함에 따라 회전속도와 모터에 흐르는 전류는 증가하였다. 인가전압이 40[Vpp] 일 때 회전속도는 206[rpm] 이며 소비전력은 0.3[W]로 제작된 시편은 카메라폰용 광학중 및 자동초점조절장치시스템 분야에 응용이 가능하다.

• Bulletin of the Korean Space Science Society
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• 2003.10a
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• pp.62-62
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• 2003

과학위성 1호에는 위성의 임무를 수행하기 위하여 광학계, 구조부, 및 전자부 등 여러가지 부품들이 실장되는데, 그 중 전자부의 가장 중요한 부품 중의 하나인 인쇄회로기판(Printed Circuit Board, PCB)의 우주환경에서의 특성 대해서 논의하고자 한다. Solder Resistor(Solder Mask)의 화학성분이 위성체가 작동하는 우주환경에서 위성체 임무수행 시 발생할 수 있는 out-gassing으로 인해 위성체가 본연의 임무 실패라는 결과를 초래할 수 있다 NASA 및 ESA의 Out-gassing에 관한 규정과 TRW에 의한 KOMSAT에 사용된 재료의 진공상태의 Outgassing에 관한 내용에 의하면, 재료의 진공상태와 Out-gassing은 America Society for Testing and Materials에서 제시한 ASTM E959 기준에 따라 제작된다. 일반적으로 우주 환경에서 광학계나 전자부의 원활한 동작을 위해서는 인쇄 회로 기판의 총 질량손실(Total Mass Loss, TML)은 1.00%을 넘지 말아야 하며, 휘발성 응축 질량 (Collected Volatile Condensable Mass, CVCM)은 0.1% 미만이어야 한다. Total Mass Loss(TML) 방법은 대기중에서 측정한 질량과 진공 조건에서 변화되는 질량을 측정함으로써 진공조건에서의 탈기체 특성을 측정하는 방법이다. 본 연구에서는 Solder Resistor(Solder Mask)의 탈기체 측정을 위한 진공챔버의 측정방법 및 진공 형성 과정을 기술하고 실제 과학위성1호에 장착될 시료를 예로 들어 인쇄회로기판에 입힌 Solder Resistor(Solder Mask)가 우주환경인 진공상태에서 위성체 부품의 작동 시 발생할 수 있는 탈기체되는 정도를 질량의 변화분으로 측정하여 위성체가 우주 환경에서 본연의 임무를 안전하게 수행할 있는지를 검증하였다.부분이다.다.향을 해석하고 시뮬레이션 하였다.Device Controller)는 ECU로부터 명령어를 받아서 arm 및 safe 상태에 대한 텔리 메트리 데이터를 제공한다 그리고, SAR(Solar Array Regulator)는 ECU로부터 Bypass Relay 및 ARM Relay에 관한 명령어를 받아 수행되며 그에 따른 텔리 메트리 데이터를 제공한다. 마지막으로 EPS 소프트웨어를 검증하는 EPS Software Verification을 수행하였다 전력계 소프트웨어의 설계의 검증 부분은 현재 설계 제작된 전력계 .소프트웨어의 동작 특성 이 위성 의 전체 운용개념과 연계하여 전력계 소프트웨어가 전력계 및 위성체의 요구조건을 만족시키는지를 확인하는데 있다. 전력계 운용 소프트웨어는 배터리의 충ㆍ방전을 효율적으로 관리해 3년의 임무 기간동안 위성체에 전력을 공급할 수 있도록 설계되어 있다this hot-core has a mass of 10sR1 which i:s about an order of magnitude larger those obtained by previous studies.previous studies.업순서들의 상관관계를 고려하여 보다 개선된 해를 구하기 위한 연구가 요구된다. 또한, 준비작업비용을 발생시키는 작업장의 작업순서결정에 대해서도 연구를 행하여, 보완작업비용과 준비비용을 고려한 GMMAL 작업순서문제를 해결하기 위한 연구가 수행되어야 할 것이다.로 이루어 져야 할 것이다.태를 보다 효율적으로 증진시킬 수 있는 대안이 마련되어져야 한다고 사료된다.$\ulcorner$순응$\lrcorner$의 범위를 벗어나지 않는다. 그렇기 때문에도 $\ulcorner$순응$\lrcorner$과 $\ulcorner$표현$\lrcorner$의 성격과 형태를 외형상으로

• Journal of Energy Engineering
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• v.29 no.2
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• pp.68-78
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• 2020

According to the new climate change agreement, technology development to reduce greenhouse gases is actively conducted worldwide, and research on energy efficiency improvement in the field of power generation and transmission and distribution is underway [1,2]. Economic analysis of the operation method of storing and supplying surplus electricity using energy storage devices, and using energy storage devices as a frequency adjustment reserve power in regional cogeneration plants has been reported as the most profitable operation method [3-7]. Therefore, this study conducted an economic analysis for the installation of energy storage devices in the combined heat and power plant in the Czech Republic. The most important factor in evaluating the economics of battery energy storage devices is the lifespan, and the warranty life is generally 10 to 15 years, based on charging and discharging once a day. For the simulation, the ratio of battery and PCS was designed as 1: 1 and 1: 2. In general, the primary frequency control is designed as 1: 4, but considering the characteristics of the cogeneration plant, it is set at a ratio of up to 1: 2, and the capacity is simulated at 1MW to 10MW and 2MWh to 20MWh according to each ratio. Therefore, life was evaluated based on the number of cycles per year. In the case of installing a battery energy storage system in a combined heat and power plant in the Czech Republic, the payback period of 3MW / 3MWh is more favorable than 5MW / 5MWh, considering the local infrastructure and power market. It is estimated to be about 3 years or 5 years from the simple payback period considering the estimated purchase price without subsidies. If you lower the purchase price by 50%, the purchase cost is an important part of the cost for the entire lifetime, so the payback period is about half as short. It can be, but it is impossible to secure profitability through the economy at the scale of 3MWh and 5MWh. If the price of the electricity market falls by 50%, the payback period will be three years longer in P1 mode and two years longer in P2 and P3 modes.

• Journal of the Korean Electrochemical Society
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• v.8 no.4
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• pp.181-185
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• 2005

Lithium cobalt oxide thin film cathode, having thickness of $2.9{\mu}m$ with area of $4cm^2$, was deposited on platinum patterned alumina substrate by radio frequency magnetron sputtering. Li/Co molar ratio, which is an important factor for battery performance, was measured as a function of argon working pressure and applied R.F. power. Constant current charge and discharge performances were characterized with high rate discharge and cycling behavior. Using AC impedance analysis, internal resistance of the thin film battery was measured and simulated by proposed equivalent circuit model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1010-1019
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• 2004

In this paper, we represent Nakagami-m fading channel as finite-State Markov Channel (FSMC) and analyze the performance of wireless communication system with varying the fading channel condition. In FSMC model, the received signal's SNR is divided into finite intervals and these intervals are formed into Markov chain states. Each state is modeled by a BSC and the transition probability is dependent upon the physical characterization of the channel. The steady state probability and average symbol error rate of each state and transition probability are derived by numerical analysis and FSMC model is formed with these values. We found that various fading channels can be represented with FSMC by changing state transition index. In fast fading environment in which state transition index is large, the channel can be viewed as i.i.d. channel and on the contrary, in slow fading channel where state transition index is small, the channel can be represented by simple FSMC model in which transitions occur between just adjacent states. And we applied the proposed FSMC model to analyze the coding gain of random error correcting code on various fading channels via computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.118-125
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• 2006

A new error amplifier is presented for fast transient response of DC-DC converters. The amplifier has low quiescent current to achieve high power conversion efficiency, but it can supply sufficient current during large signal operation. Two comparators detect large-signal variations, and turn on extra current supplier if necessary. The amount of extra current is well controlled, so that the system stability can be guaranteed in various operating conditions. The simulation results show that the new error amplifier achieves significant improvement in transient response than the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.1-8
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• 2004

A novol clock distribution scheme is proposed for high-speed and low-power digital system to minimize clock skew and reduce dynamic power consumption. This scheme has ideal zero-skew characteristic by using folded clock lines (FCL) and phase blending circuit. For analyzing suitable line structures to FCLs, microstrip line and coplanar line are placed with folded clock lines. Simulation results show that the maximum clock-skew between two receivers located 10mm apart is less than lops at 1㎓ and the maximum clock-skew between two receivers located 20mm apart is less than 60ps at 1㎓. Also the results show that the minimum skews of clock signals regardless of process, voltage, and temperature variation are invariant.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.