• Journal of Navigation and Port Research
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• v.27 no.5
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• pp.505-511
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• 2003

In this paper, a driving amplifier stage with 1 Watt output has been designed and fabricated, which is operating at UHF band( 470 ∼ 806 MHz) for digital TV repeater. In the driving amplifier stage, preamplifier and 1 Watt unit amplifier are integrated by one electric substrate which is 2.53 in dielectric constant and 0.8 mm thickness. When the driving amplifier stage is flown by bias voltage of 28 V DC and current of 900 mA. it has the gain of more than 53.5 dB. the gain flatness of $\pm$0.5 dB and return loss of less than -15 dB in 470 ∼ 806 MHz. Also, when two signals at 2 MHz frequency interval are input port into the driving amplifier stage with 1 Watt output, it resulted in excellent characteristics to designed specification with showing intermodulation distortion characteristics of more than 48 dBc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2267-2272
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• 2009

The six-port direct conversion receiver front-end that is comprised of a carrier recovery and a phase shifter, which gets the same structure with six-port phase correlator using the multi-layer coupled line, was designed and fabricated in this paper. The six-port element that is comprised of the power divider and the hybrid coupler is designed by multi-layer coupled line structure. The multi-coupled structure is utilized as the basic structure in receiver phase correlator, carrier recovery circuit and phase shifter. The receiver front-end with the same multi-layer coupled line structure for the receiver elements shows the simple structure and no difficulty in integration. The fabricated multi-layer coupled six-port receiver front-end re-generates the carrier signal with a constant phase and demodulates the PSK transmission signal.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.985-991
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• 2008

This paper presents a novel balanced mixer receiver front-end design based on a metamaterial structure applicable to differential-/common-mode excitation. This metamaterial structure functions as a leaky-wave antenna and provides in-trinsic common-mode suppression. Low LO leakage and high RF to LO isolation are achieved without additional filters for LO and RF paths. The metamaterial is based on a unit-cell which under a differential-mode excitation behaves like a composite right/left-handed(CRLH) metamaterial. In contrast, the metamaterial unit-cell is below cut-off under a common-mode excitation. Experimental results are used to verify the proposed metamaterial's differential-/common-mode characteristics. The metamaterial is integrated with a balanced mixer design resulting in an operation frequency range of $1.96{\sim}2.40$ GHz with an optimum mixer conversion loss of 21.1 dB at 2,4 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.442-446
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.11
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• pp.34-39
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• 2002

In this paper, we proposed novel photonic bandgap(PBG) structure using EGP(Elevated Ground Plane) and via in ceramic substrate of microstrip line. From analysis result, the proposed PBG structure is reduced 52.5% at size and increased 45 % at bandwidth compared to typical planar PBG structure. It is also reduced 32 % at size and improved more than 8 dB at power loss compared to typical multilayer DGS(Defected Ground Structure). The proposed PBG structure also can be used bandstop and lowpass filter and it will be useful for small microwave integrated circuit and module development.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.238-239
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• 2011

최근 반도체 산업은 더 높은 성능의 회로 제작을 통해 초고집적화를 추구하고 있다. 이를 위해서 회로 설계의 최소 선폭과 소자 크기는 지속적으로 감소하고 있고 이를 위한 배선 기술들은 플라즈마 공정을 이용한 식각공정에 크게 의존하고 있다. 식각공정에 있어서 반응가스의 조성은 식각 속도와 선택도를 결정하는 중요한 요소이다. 본 연구에서는 CIS QMS (closed ion source quadrupole mass spectrometer)를 이용하여 CF4+Ar를 이용한 실리콘 산화막의 플라즈마 식각 공정 시 생성되는 라디칼과 이온 종들을 측정하였다. Ar 이온이 기판표면과 충돌하여 기판물질간의 결합을 깨놓으면, 반응성 기체 및 라디칼과의 반응성이 커져서 식각 속도를 향상 시키게 된다. 본 실험에서는 2 MHz의 RPS (remote plasma source)를 이용하여 플라즈마를 발생시키고 13.56 MHz의 rf 전력을 기판에 인가하여 식각할 웨이퍼에 바이어스 전압을 유도하였다. CF4/(CF4+Ar)의 가스 혼합비가 커질수록 식각 부산물인 SiF3의 양은 증가 하였으며, CF4 혼합비가 0일 때(Ar 100%) 비하여 1일 때(CF4 100%) SiF3의 QMS 이온 전류는 106배 증가하였다. 이때의 Si와 결합하여 SiF3를 형성하는 F라디칼의 소모는 0.5배로 감소하였다. 또한 RPS power가 800 W일 때 플라즈마에 의해서 CF4는 CF3, CF2, CF로 해리 되며 SiO2 식각 시 라디칼의 직접적인 식각과 Si_F2의 흡착에 관여되는 F라디칼의 양은 CF3 대비 7%로 검출되었고, 식각 부산물인 SiF3는 13%로 측정되었다. Ar의 혼합비를 0 %에서 100%까지 증가시켜 가면서 측정한 결과 F/CF3는 $1.0{\times}105$에서 $2.8{\times}102$로 변화하였다. SiF3/CF3는 1.8에서 6.3으로 증가하여 Ar을 25% 이상 혼합하는 것은 이온 충돌 효과에 의한 식각 속도의 증진 기대와는 반대로 작용하는 것으로 판단된다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.548-553
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• 2004

In this paper, single, two, and three-section microstrip directional couplers are implemented for realizing the high directivity characteristics. The achievement of the high directivity with microstrip configuration is carried out by the distributed capacitor to decrease the even and odd mode phase difference. Capacitive compensation is performed by gap coupling of open stub formed in sub-coupled line. Therefore, insertion loss and power handling capability are not affected by the gap coupling. The proposed structure is easy to fabricate and incorporate another microwave device due to the planner microstrip. We designed and fabricated single, two, and three-section directional coupler with 20 ㏈ coupling. In spite of microstrip structure, the capacitive compensation structure shows 30 ㏈, 27 ㏈, and 25 ㏈ of directivity in single, two, and three-section directional couplers, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.216-219
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• 2016

In this paper, the SIW(Substrate Integrated Waveguide)-based feeding antenna for the application of SDR(Software Defined Radar) is designed and manufactured. It is usually well-known that SIWs are easily integrated on PCB and have low transmission loss toward high powered input signal. Also, it is recommended that SIWs are strongly immunized to Electromagnetic Interferences(EMI). In particular, the manufactured antennas are loaded on the USRP(Universal Software Radio Peripheral) platform and employed to detect target RCS as an experiment in this paper. The operating frequency of the proposed antenna is in ISM(Industrial, Scientific and Medical) band(2.4~2.48 GHz) and the measured gain is over 8 dBi at 2.44 GHz.