• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.72-79
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• 2003

Classical designs of optical transimpedance preamplifier for p-i-n photodiode receiver circuits generally employ common source transimpedance input stages. In this paper, we explore the design of a class of current-mode optical transimpedance preamplifier based upon common gate input stages. A feature of current-mode optical transimpedance preamplifier is high gain and high bandwidth. The bandwidth of the transimpedance preamplifier can also be increased by the capacitive peaking technique. In this paper we included the development and application of a circuit analysis technique based on the minimum noise. We develop a general formulation of the technique, illustrate its use on a number of circuit examples, and apply it to the design and optimization of the low-noise transimpedance amplifier. Using the noise minimization method and the capacitive peaking technique we designed a transimpedance preamplifier with low noise, high-speed current-mode transimpedance preamplifier with a 1.57GHz bandwidth, and a 2.34K transimpedance gain, a 470nA input noise current. The proposed preamplifier consumes 16.84mW from a 3.3V power supply.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.4
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• pp.263-269
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• 2008

In this paper, an interleaved boost converter (IBC) with ZVT cell using a single resonant inductor in continuous conduction mode (CCM) is proposed. The IBC with the proposed ZVT cell has advantages such as a simple circuit, reduced size and low cost by using a single resonant inductor. It is more suitable for high power applications. The proposed ZVT cell circuit and principles for the IBC are explained in detail. The validity of the IBC with proposed ZVT cell is verified through experimental results.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.4
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• pp.23-28
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• 2023

In a wireless smart utility network communication system, an asynchronous low power MAC is standardized and used according to IEEE 802.15.4e. An asynchronous MAC called RIT (Receiver Initiated Transmission) has a characteristic in which delay time and power consumption are greatly affected by a check-in interval (RIT period). By waking up from sleep every check-in interval and checking whether there is data to be received, power consumption in the receiving end can be drastically reduced, but power consumption in the transmitting end occurs due to an excessive wakeup sequence. If an excessive wake-up sequence is reduced by shortening the check interval, power consumption of the receiving end increases due to too frequent wake-up. In the RIT asynchronous MAC technique, power consumption performance according to traffic load and operation of check-in interval is analyzed and applied to Wi-SUN construction.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.1-10
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• 1999

A low power concumption 2.4 GHz one-chip transceiver MMIC was designed and fabricated using $1.0\mu\textrm{m}$ ion-implantation MESFET process and packaged on a 24 lead SSOP. In the transmitter mode, it revealed conversion gain of 7.5 dB, output IP3 of -3.5 dBm, and noise figure of 3.9 dB at 2.44 GHz with 3.9 mA current consumption. In the receiver mode, it revealed voltage sensitivity of 6.5 mV/$\mu\$W with 2 .0 mA current consumption. Comparing the fabricated MMIC with the results of MMICs reported elsewhere, it was shown that the fabricated MMIC had good performance. The low power consumption 2.4 GHz transceiver MMIC is expected to be used for various applications such as wireless local area networks, wireless local loops and RFID tags in ISM-band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.47-55
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• 2005

This work describes an 8b 240 MS/s CMOS ADC as one of embedded core cells for high-performance displays requiring low power and small size at high speed. The proposed ADC uses externally connected pins only for analog inputs, digital outputs, and supplies. The ADC employs (1) a two-step pipelined architecture to optimize power and chip size at the target sampling frequency of 240 MHz, (2) advanced bootstrapping techniques to achieve high signal bandwidth in the input SHA, and (3) RC filter-based on-chip I/V references to improve noise performance with a power-off function added for portable applications. The prototype ADC is implemented in a 0.18 um CMOS and simultaneously integrated in a DVD system with dual-mode inputs. The measured DNL and INL are within 0.49 LSB and 0.69 LSB, respectively. The prototype ADC shows the SFDR of 53 dB for a 10 MHz input sinewave at 240 MS/s while maintaining the SNDR exceeding 38 dB and the SFDR exceeding 50 dB for input frequencies up to the Nyquist frequency at 240 MS/s. The ADC consumes, 104 mW at 240 MS/s and the active die area is 1.36 ㎟.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.31-37
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• 2001

Digital servo implementation in optical servo chip has been spotlighted since it is easy to integrate with other blocks and it has less sensitive characteristics change in terms of temperature variation and better flexibility to the system variation like pick-up. Therefore, Optical disc players adopted digital servo are increasing in market. However, one drawback of digital signal processor embedded digital servo is power consumption that is one of the most important factors of portable optical disc player system. For that reason, this paper introduces new architecture to reduce power consumption of digital servo by means of reducing DSP load but increasing minimum hardware size. The main idea of reducing power consumption of digital servo greatly is utilizing CDP characteristics as most operations are done and used up most operating steps of DSP at the initial time, but most power consumption is occurred in play mode. Therefore, if operating steps for digital filtering in play mode could be reduced greatly, power consumption of overall system can be reduced greatly. This paper shows an example that low power digital servo architecture whose current is reduced almost 83%, compare to that of digital servo which is not applied by the low power architecture introduced in this paper.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.669-672
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• 2015

Recent Internet of Things (IoT, Internet of Things) that can be applied to various fields as the development of technology has been developed a lot of service and has been developed with the service also for crop management. To manage the essential elements of soil moisture in the crop growth but existing a direct person measuring the fluid point to carry the measuring instrument, if you take advantage of the WPAN (Wireless Personal Area Network) in this paper to manage sensor data, a fixed 3 points (30, 60, 90 cm) and can be managed can be scientifically analyzed the state of growth of the crop. Open field environment is utilized as it is less disturbance of the interference and the frequency of the radio frequency signal of the structure provides a relatively comfortable environment. Therefore, WPAN building and data transmission scheme of the minimum cost is to be developed. In addition, the operation to enter low power mode, the algorithm is necessary because a lot of restrictions on the power supply applied to the sensor nodes and the gateway is constructed in the open field. In the experiment, verifying the effectiveness by using a network configuration of each of the sensor nodes and the gateway, and provides a method for time synchronization of the operation and a low power mode. The study protocol for the RF communication with the LoRa and to enhance communication efficiency is needed in the future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.487-494
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• 2020

In this paper, we propose a current memory circuit design that reduces static power consumption and maximizes the advantages of current mode signal processing. The proposed current memory circuit minimizes the problem in which the current transfer error increases as the data transfer time increases due to clock-feedthrough and charge-injection of the existing current memory circuit. The proposed circuit is designed to insert a support MOS capacitor that maximizes the Miller effect in the current transfer structure capable of low-power operation. As a result, it shows the improved current transfer error according to the memory time. From the experimental results of the chip, manufactured with MagnaChip / SK Hynix 0.35 process, it was verified that the current transfer error, according to the memory time, reduced to 5% or less.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.431-440
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• 2012

In this paper, new beam-forming array antenna is proposed. The proposed beam-forming array antenna has control ability for beam-direction/width by employing low loss reconfigurable power divide and three-dimensional array structure. The reconfigurable power divider is key idea in the proposed antenna, because it has reconfigurable RF power distribution ability to each antenna. And, for research and verification of the proposed antenna, 3-dimensional beam-forming array antenna is implemented, and the experimental results show that the proposed antenna has various radiation modes from 1:1 to 1:N by adjusting RF power distribution.