• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.575-577
• /
• 2017

In public key cryptography such as RSA, modular exponentiation is the most time-consuming operation. RSA's modular exponentiation can be computed by repeated modular multiplication. To attain high efficiency for RSA, fast modular multiplication algorithms have been proposed to speed up decryption/encryption. Montgomery multiplication is limited by the carry propagation delay from the addition of long operands. In this paper, we propose a hardware structure that reduces the area of the Montgomery multiplication implementation for lightweight applications of RSA. Experimental results showed that the new design can achieve higher performance and reduce hardware area. A frequency of 884.9MHz and 250MHz were achieved with 84K and 56K gates respectively using the 90nm technology.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.56-63
• /
• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• 한국방재학회:학술대회논문집
• /
• 2011.02a
• /
• pp.161-161
• /
• 2011

지진, 산사태, 액상화 등의 지질재해 예측을 위한 지역적 지반특성을 규명하기 위해서 지질도 또는 지형도를 이용하여 간접적인 방법이 사용되기도 한다. DEM에서 추출한 경사도는 지반분류 시 하나의 기준으로 사용되어질 수 있고, 이때 DEM의 해상력에 따라 그 결과가 다르게 산출될 수도 있다. 이번 연구에서는 DEM의 해상력에 따라 우리나라 일부지역의 지반분류 결과에 어떤 영향을 미치는지 살펴보았다. 각기 다른 해상도의 DEM을 적용하여 우리나라 동남부 지형을 경사도 기준으로 지반분류한 후 그 면적차이를 해상도별로 비교한 결과, 지반분류 C 지역의 면적 변화가 가장 뚜렷하였다. $V_s30$ 범위로 분류한 결과에서는 180 m/sec 이하의 지역에서 해상도별로 가장 큰 변화가 있었다. 고해상도에서는 지반분류 B와 E의 지역에서 면적이 저해상도 보다 크게 산출되는 경향이 있었고, 저해상도에서는 지반분류 C와 D 지역의 면적이 고해상도 보다 크게 산출되는 경향이 있었다. 이는 DEM의 해상도가 낮아질수록 각기 다른 지반정보를 함유한 작은 셀이 큰 셀로 만들어지는 과정에서 평균화되는 지반정보가 과대평가 또는 저평가되었기 때문이다. 연구지역 내 시추지역의 지반과 지반분류 결과를 비교하면 해상도별로 78%~52%까지 일치하였고, 고해상도에서 일치율이 더 높았다. 지형의 변화가 심하고 인구나 산업시설이 밀집된 재해 고위험군 지역은 고해상도의 지도를 이용하고, 지형의 변화가 없거나 단단한 지반의 지역은 재해가 상대적으로 작아서 저해상도의 사용으로 자료처리 시간의 효율성을 증대시키는 방안도 생각할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.8B
• /
• pp.1477-1486
• /
• 2000

This paper proposes an efficient kernel-based partitioning algorithm for reducing area and power dissipation in combinational circuit design.. The proposed algorithm decreases the power consumption by partitioning a given circuit utilizing a kernel, and reduces the area overhead by minimizing duplicated gates in the partitioned subcircuits. Experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating circuits consuming 43.6% less power with 30.7% less area on the average, when compared to the previous algorithm based on precomputation circuit structure.

• Proceedings of the KIEE Conference
• /
• 2006.07c
• /
• pp.1639-1640
• /
• 2006

MEMS형 써모파일은 온도계, 유속, 가스, 칼로리미터 등 다양한 산업 분야에 응용되고 있다. 현재 상용화되어 있는 대부분의 MEMS형 써모파일에서는 습식 이방성 에칭방식으로 다이어프램을 제작하고, 막의 구성은 산화막/질화막/산화막 혹은 산화막/질화막의 적층으로 되어 있다. 본 논문에서는 $XeF_2$시스템을 사용해 전면으로부터 에칭하여 저응력 질화막을 다이어프램을 제작하였고, 열전대 물질로는 poly-Si과 Al을 사용하였다. 그리고 각각의 열전쌍은 열접점에서 Al 패턴시, 사각형의 오픈 면적을 두어 접합된 모양을 달리하여 설계 제작하였다. 소자의 크기는 $2{\times}2mm^2$이고, 능동영역은 $400{\times}400{\mu}m^2$이다. 써모파일의 출력은 적외선 램프의 전력이 3W($80^{\circ}C$)일 때, 오픈된 면적이 증가할수록 출력이 증가하였으며, 오픈된 면적이 $300{\mu}m^2$ 일때의 출력은 약1mV로 나타났다. 이러한 특성으로부터 계산된 오픈된 면적에 따른 출력비는 약 $0.3nV/{\mu}m^2$이다.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.18 no.7
• /
• pp.548-553
• /
• 2017

The aim of this study was to develop a low impact development design technique that can be applied in the land use planning stage and verify quantitatively the effects of non-point pollution reduction. For this purpose, the low impact development design elements that can be applied in the land use planning stage were derived and applied to an actual site, and the non-point pollution reduction effect was analyzed using the LIDMOD2 program. The analysis showed that the permeability rate of the land use plan using low impact development decreased by 19.8% compared to the existing land use plan. In addition, annual surface runoff decreased by 19.0% and annual infiltration increased by 164.1%. In the case of non-point pollution, the annual loading, T-N, T-P, and BOD decreased by 18.7 ~ 22.8%. Therefore, compared to the existing land use plan, the land use plan using low impact development has a considerably large effect of reducing the non-point pollution without changing the floor area according to each application. Therefore, to maximize the reduction effect of non-point pollution, it will be necessary to establish a related plan by applying the low impact development technique from the land use planning stage to the existing LID facility-oriented plan.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.60-67
• /
• 2008

A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

• Journal of IKEEE
• /
• v.7 no.1 s.12
• /
• pp.9-15
• /
• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.

• Journal of the Society of Disaster Information
• /
• v.9 no.1
• /
• pp.56-64
• /
• 2013

The study examines the quiet pavement using fine-size aggregates and warm-mix technique to reduce traffic noise. In order to evaluate the quality of pavement, mix design and laboratory tests were carried out. Test results showed that using 10mm aggregates can reduce the cantabro loss compared with 13mm aggregates due to increase contact area between aggregates. Mixing and compaction temperatures of warm mix quiet pavement should be determined by gyratory compactor test because it is used high viscosity asphalt binder. Using warm-mix additive could reduce compaction temperature by about $15^{\circ}C$. Noise measurement and permeability tests were conducted at the test road for evaluation of the field performance. All of quiet pavements meet the standard of permeability and have sufficient porosity. Noise reduction of the quiet pavement using fine-size aggregates is more effective than that using 13mm aggregates. In particular, the effect of noise reduction was noticeable at low speeds.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.93-101
• /
• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.