• Title/Summary/Keyword: 저면적

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Low-cost Assessment of Canopy Light Interception and Leaf Area in Soybean Canopy Cover using RGB Color Images (RGB 컬러 이미지를 이용한 콩의 군락 피복과 엽면적에 대한 저비용 평가)

  • Lee, Yun-Ho;Sang, Wan-Gyu;Baek, Jae-Kyeong;Kim, Jun-Hwan;Cho, Jung-Il;Seo, Myung-Chul
    • Korean Journal of Agricultural and Forest Meteorology
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    • v.22 no.1
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    • pp.13-19
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    • 2020
  • This study compared RGB color images with canopy light interception (LI) and leaf area index (LAI) measurements for low cost and low labor. LAI and LI were measured from vertical gap fraction derived from top of digital image in soybean canopy cover (cv Daewonkong, Deapongkong and Pungsannamulkong). RGB color images, LAI, and LI were collected from V4.5 stage to R5stage. Image segmentation was based on excess green minus excess red index (ExG-ExR). There was a linear relationship between LAI measured with LI (r2=0.84). There was alinear relation ship between LI measured with canopy cover on image (CCI) (r2=0.94). There was a significant positive relationship(r2=0.74) between LAI and CCI at all grow ingseason. Therefore, it is expected that in the future, the RGB color image could be able to easily measure the LAI and the LI at low cost and low labor.

A Hardware Design Space Exploration toward Low-Area and High-Performance Architecture for the 128-bit Block Cipher Algorithm SEED (128-비트 블록 암호화 알고리즘 SEED의 저면적 고성능 하드웨어 구조를 위한 하드웨어 설계 공간 탐색)

  • Yi, Kang
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.4
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    • pp.231-239
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    • 2007
  • This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.

재건축 아파트 규모별 안전 문제점

  • 박경태;손기상
    • Proceedings of the Korean Institute of Industrial Safety Conference
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    • 2001.11a
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    • pp.186-190
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    • 2001
  • 국내의 재건축은 80년대 후반부터 황금알을 낳는 거위로 인식되어 붐을 일으키는 과정에서 공사부실, 분양사기 등 우여곡절을 겪고 또한 경기 부침에 따라 선호도나 경제성에 좌우되는 어려움을 겪어왔다. 정부의 전용면적 18평 이하 저평수 건설의무화로 건설업체의 수익성 악화 우려로 건설기피현상을 보게 되었고, 그 규제가 해제되었다가 다시 20%가 의무화되었다.(중략)

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Rearing Density of a Flounder, Paralichthys olivaceus Juveniles in a Closed Recirculating Sea Water System - Possibility of High-density Rearing - (폐쇄순환여과시스템에서의 넙치, Paralichthys olivaceus 치어의 사육밀도 - 고밀도사육의 가능성 -)

  • CHANG Young Jin;YOO Sung Kyoo
    • Journal of Aquaculture
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    • v.1 no.1
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    • pp.13-24
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    • 1988
  • In order to investigate a reasonable rearing density and the possibility of high-density rearing, flounder, Paralichthys olivaceus, juveniles of 2.53$\pm$0.24 cm in total length and 1.12$\pm$0.12 cm in body height were used in this study. The initial rearing density of them was 10 (D10), 20 (D20), 30 (D30) and 40 (D40) individuals per 137.75 $cm^2$ of bottom area, respectively. Ranges of water temperature and specific gravity during the rearing period of 65 days were $21.0\~27.0^{\circ}C$ and 1.024$\~$1.026, respectively, showing relatively higher values than that of natural sea water. Dissolved oxygen during the rearing period was 5.4$\~$7.5 ml/$\iota$ and inorganic nitrate was 0.07$\~$0.48 ppm in $NH_4^+-N$, 0.006$\~$0.33 ppm in $NO_2^{-}-N$ and 3.89$\~$34.06 ppm in $NO_3^{-}-N$. Growth in total length and body height of the juveniles in four rearing density at the end of the experiment was 8.17$\pm$0.80 em and 4.16$\pm$0.39 em, the highest in D20 and 7.72$\pm$0.40 cm and 3.94$\pm$0.21 cm, the lowest in D10. Significant differences, however, were not recognized between the slope values of growth regressions in four rearing density. Slope values of the relative growth between total length and body height of the juveniles in four rearing density were 0.5346, the highest in D10 and 0.5165, the lowest in D30, but there were no significant differences in those values. Survival rate of juveniles at the end of the experiment was $90\%$ in D10, D20 and D30, but that of D40 was $75\%$. The relationship between total length X body height (X) and body surface area of ocular side (Y) to calculate the rate of Y to bottom area in rearing tank (covering rate) as an indicator of rearing density was expressed by a linear regression, Y=0.5994X+0.1840. Covering rate in four rearing density at the end of the experiment was ranged 1.2$\~$4.1 times. Judging from the covering rate above 4 times, it seems to be possible rearing the flounder juveniles in high-density.

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Design of 94-GHz High-Gain Differential Low-Noise Amplifier Using 65-nm CMOS (65-nm CMOS 공정을 이용한 94 GHz 고이득 차동 저잡음 증폭기 설계)

  • Seo, Hyun-woo;Park, Jae-hyun;Kim, Jun-seong;Kim, Byung-sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.29 no.5
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    • pp.393-396
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    • 2018
  • Herein, a 94-GHz low-noise amplifier (LNA) using the 65-nm CMOS process is presented. The LNA is composed of a four-stage differential common-source amplifier and impedance matching is accomplished with transformers. The fabricated LNA chip shows a peak gain of 25 dB at 94 GHz and has a 3-dB bandwidth at 5.5 GHz. The chip consumes 46 mW of DC power from a 1.2-V supply, and the total chip area, including the pads, is $0.3mm^2$.

A 6Gbps CMOS Feed-Forward Equalizer Using A Differentially-Connected Varactor (차동 연결된 Varactor를 이용한 6Gbps CMOS 피드포워드 이퀄라이저)

  • Moon, Yong-Sam
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.2
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    • pp.64-70
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    • 2009
  • A 6-Gbps feed-forward equalizer having a 6.2-dB gain at 3GHz is designed in 0.13-um CMOS technology and the equalizer helps error-free data recovery over a 7-m SATA cable with 14.7dB loss. Based on a differentially-connected varactor, the proposed equalizer uses only a one-fourth varactor size of a conventional equalizer, which enables the equalizer's integration in a pad-frame, high operating frequency, and low power dissipation of 3.6mW.

대면적 터치스크린용 Index Matching ITO Galss 개발

  • Jeong, Dong-Hwa;Jeong, Jong-Guk;Kim, Chang-Gyu;Jo, Won-Seon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.339.2-339.2
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    • 2014
  • 터치패널은 저항막 방식, 정전용량 방식, 적외선방식, Camera방식 등을 사용하고 있으며 현재 널리 상용화 되어 있는 방식은 정전용량 방식이다. 최근 터치스크린의 면적이 점점 커지게 되면서 점차 저저항, 고투과율을 가지는 IM ITO (Index matching ITO)를 요구하고 있다. 본 연구에서는 중대형 사이즈(15inch 이상)의 Cover glass 일체형 터치센서 구현을 위한 저저항(60ohm/sq이하), 고투과(88% 이상)의 IMITO Glass를 제작하여 전기적,광학적 특성을 분석하여 IMITO 성막조건을 최적화시키는 연구를 하였다. 또한 TSP의 Pattern 시인성을 향상시키기 위해 Index matching층을 고굴절재료와 저굴절 재료를 사용한 다층박막을 형성하여 반사율(0.5% 이하)을 최소화시켜 구현하였다.

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Design of ENMODL CLA for Low Power High Speed Multiplier (고속 저전력 곱셈기에 적합한 ENMODL CLA 설계)

  • 백한석;진중호;송관호;문성룡;한석붕;김강철
    • Proceedings of the Korea Institute of Convergence Signal Processing
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    • 2001.06a
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    • pp.93-96
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    • 2001
  • 본 논문에서는 고속 저전력 곱셈기에 적합한 CPA(Carry Propagation Adder)부분의 ENMODL (Enhanced NORA MODL) 설계방식을 제안한다. ENMODL 설계방식은 반복성이 많은 CLA(Carry-Look-ahead Adder) 가산기와 같은 회로에서 많은 면적을 줄일 수 있고 동작 속도를 빠르게 할 수 있다. 따라서 본 논문에서는 저전력 고속 곱셈기에 적합한 CPA 부분을 ENMODL CLA 가산기로 설계했고 현대 0.6$\mu\textrm{m}$ 2-poly 3-metal 공정파라미터를 이용하여 HSPICE로 시뮬레이션 하여 회로의 성능을 확인하였다. 또한, CADENCE tool을 이용하여 16비트 곱셈기에 적합한 ENMODL CLA를 레이아웃 하여 칩 제작 중에 있다.

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Low-power Digital Down Conversion filter design for Multi-mode (Multi-mode용 저전력 Digital Down Conversion filter 설계)

  • Kim, Do-Han;Hur, Eun-Sung;Jang, Young-Beom
    • Proceedings of the IEEK Conference
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    • 2007.07a
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    • pp.75-76
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    • 2007
  • 이 논문에서는 IS-95와 WCDMA의 Multi-mode로 동작하는 Multi-mode용 저전력 DDC filter 구조를 제안한다. 기존의 DDC구조의 경우 CIC의 통과대역 특성을 향상시켜 주지만, 저지대역의 감쇠특성은 오히려 나빠지는 문제점을 안고 있었다. 제안된 구조는 CIC 데시메이션 필터의 통과대역 특성은 더욱 향상시켜주며, 저지대역의 감쇠특성도 같이 향상시키는 특징을 가진다. 또한 제안된 절터는 각 필터의 면적을 감소시키기 위해 IS-95와 WCDMA의 각각의 모드에 대해 한 개의 필터를 설계한 후 각 모드에 따라 필터 탭 수를 달리하여 동작하는 Multi-mode의 저전력 구조로 구현하였다.

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친환경 건설정책 - 저에너지 친환경 공동주택 시대 열다 - 강동구, 저에너지 친환경 공동주택 가이드라인 확정 -

  • 대한설비건설협회
    • 월간 기계설비
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    • s.236
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    • pp.48-51
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    • 2010
  • 국토해양부(장관 정종환)는 최근 연세대 친환경건축연구센터와 서울시 강동구가 협의('09.8)를 통해 친환경 공동주택 가이드라인을 마련함에 따라 강동구부터 '저에너지 친환경 공동주택 가이드라인' 시행에 들어 간다고 밝혔다. 가이드라인의 주요내용은 공동주택 재건축시 냉 난방 에너지 총 소비량의 40% 이상을 절감하고, 관리동 등 공용시설의 제로에너지화, 지역특성에 맞게 생태면적률 40%이상 확보, 단지내 인공생물 서식공간 조성의 의무화 등이다. 강동구는 앞으로 지어지는 재건축정비사업의 공동주택 모두에 가이드라인 내용을 반영하여 친환경 공동 주택으로 건설을 추진할 계획이며, 특히 고덕지구($1,239,407m^2$, 18,540가구) 및 둔촌지구($626,235m^2$, 9,090가구)부터 적용하여 친환경공동주택단지를 조성할 전망이다.

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