• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.180-184
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• 2013

In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and -VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ${\mu}A$ at a 2.5 V supply voltage in active mode, and occupies $1.3mm{\times}0.5mm$ in area. In addition, it shows fast start-up time of 10 ${\mu}s$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.1-8
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• 2004

This paper proposes a novel algorithm for a low power turbo decoder based on reduction of number of decoding iterations, targeting power-critical mobile communication devices. Previous researches that attempt to reduce number of decoding iterations, such as CRC-aided and LLR methods, either show degraded BER performance in return for reduced complexity or require additional hardware resources for controlling the number of iterations to meet BER performance, respectively. The proposed algorithm can reduce power consumption without degrading the BER performance, and it is achieved with minimal hardware overhead. The proposed algorithm achieves this by comparing consecutive hard decision results using a simple buffer and counter. Simulation results show that the number of decoding iterations can be reduced to about 60% without degrading the BER performance in the proposed decoder, and power consumption can be saved in proportion to the number of decoding iterations.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.220-226
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• 2010

In this paper, an low power symbol detector is proposed for MIMO communication system with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing (SM) mode and spatial diversity (SD) mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block and using the dedicated clock MIMO modes, the power of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and synthesized to logic gates using a $0.13-{\mu}m$ CMOS standard cell library. The power consumption was estimated by using Synopsys Power CompilerTM, which is reduced by maximum 85%, compared with the conventional architecture.

• Journal of Astronomy and Space Sciences
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• v.13 no.2
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• pp.41-51
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• 1996

KITSAT-1 and 2 are microsatellites weighting 50kg and all the on-board data are processed by the on-board computer system. Hence, these on-board computers require to be highly reliable and be designed with tight power consumption, mass and size constraints. On-board computer(OBC) systems for KITSAT-1 and 2 are also designed with a simple flexible hardware for reliability and software takes more responsibility than hardware. KITSAT-1 and 2 on-board computer system consist of OBC 186 as the primary OBC and OBC80 as its backup. OBC186 runs spacecraft operating system (SCOS) which has real-time multi-tasking capability. Since their launch, OBC186 and OBC80 have been operating successfully until today. In this paper, we describe the development of OBC186 hardware and software and analyze its in-orbit operation performance.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.141-144
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• 2000

최근에 무선통신망을 이용한 데이터 서비스가 폭넓게 제공되면서, 이동체(MS:mobile station)에 대한 위치정보나 교통상황 둥의 부가 정보 서비스가 제공되고 있다. 이와 같이 이동체가 자동차와 같은 운행수단일 때 사용자가 디스플레이 되는 문자정보를 확인하게 되면 운전의 안정성이 저하되어 실용적이지 못하다. 이를 위해서 문자를 음성으로 전환하여 주는 문자-음성변환기(text to speech : TTS)가 필요하다. 본 논문은 car navigation용 '한국어 무제한 어휘 음성합성기' 를 저가의 DSP chip(ADSP-2185)과 저용량의 4M bits ROM을 사용하여 low-cost system으로 하드웨어를 구성하였다. 본 연구에서 개발된 실시간 한국어 음성 합성기는 저가의 통신 단말기로서 사용 될 수 있으나, 반음절 연결부분의 연결이 불완전한 경우가 많았다. 그러나 종성이 없는 음절에 대해서는 명료도가 비교적 우수하였다.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.113-116
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• 2001

제로트리 부호화 알고리즘 중 효율적이며 잘 알려진 SPIHT는 높은 메모리 요구로 인해 하드웨어 구현에 큰 어려움을 가지고 있다. 이 논문에서는 저 메모리 사용과 빠른 제로트리 부호화 알고리즘을 제안한다. 메모리를 줄이고 빠른 코딩을 위한 방법으로 다음 3가지를 사용한다. 첫 번째, 리프팅을 이용한 웨이블릿 변환은 기존의 필터뱅크 방식의 변환보다 저 메모리와 계산량의 감소를 가진다. 두 번째, 웨이블릿 변환된 계수들은 블럭으로 나누어져 각각 코딩된다. 여기서 블록은 제로트리 구조가 유지되는 STB(spatial tree-based block)이다. 세 번째, Wheeler 와 Pearlman이 제안한 NLS (no list SPIHT)를 이용한 부호화이다. NLS는 효율성에서 SPIHT와 거의 같으며 작고 고정된 메모리와 빠른 부호화 속도를 보여준다.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.7-8
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• 2017

최근 ARM 프로세서의 가상화 확장 기술을 이용하는 임베디드 시스템에서 다종의 OS 작동을 지원하는 하이퍼바이저가 많이 개발되었다. 가상화 기술은 하드웨어 자원을 효과적으로 사용한다는 이점이 있지만, RTOS를 작동시킬 경우 하이퍼바이저의 오버헤드에 의해 RTOS의 성능이 저하될 수 있는 문제가 발생한다. 본 논문에서는 가상화 기술을 지원하는 ARMv7 Cortex-A15 프로세서를 탑재한 NVidia Jetson TK-1 임베디드 보드에서 RTOS가 단독으로 작동했을 때의 성능과 QPlus Hypervisor를 통해 Linux OS와 함께 RTOS가 작동했을 때의 성능을 측정하고 비교 분석 하였다.