• Proceedings of the Korean Society of Computer Information Conference
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• 2015.07a
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• pp.202-203
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• 2015

무선 센서 네트워크는 제약된 하드웨어와 개방된 환경으로 인해 싱크 홀 공격에 취약한데 이를 위해서 INSENS가 제안되었다. 이러한 INSENS는 베이스 스테이션과 센서 노드들 사이에 거리를 기반으로 경로를 설정하므로 이벤트가 자주 발생할 경우 특정 경로에 노드들은 트래픽이 증가하여 에너지 불균형을 가진다. 이러한 문제점을 해결하기 위해 본 논문에서는 네트워크 상황을 고려하여 균형적으로 에너지를 소모하게 하는 퍼지 시스템 기반의 효율적인 경로 설정 방법을 제안한다. 퍼지 시스템은 배터리 잔량, 홉 수, 경로설정 횟수의 입력을 통해 네트워크의 효율적인 경로를 설정한다. 그러므로 제안 기법은 효율적인 경로 선택으로 트래픽을 분산시켜 전체 센서 네트워크의 수명을 연장한다.

• Journal of IKEEE
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• v.26 no.2
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• pp.313-318
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• 2022

The feedback voltage detection structure is proposed to alleviate overshoot and undershoot caused by the removal of the existing external output capacitor. Conventional LDO regulators suffer from overshoot and undershoot caused by imbalances in the power supply voltage. Therefore, the proposed LDO is designed to have a more improved transient response to form a new control path while maintaining only the feedback path of the conventional LDO regulator. A new control path detects overshoot and undershoot events in the output stage. Accordingly, the operation speed of the pass element is improved by charging and discharging the current of the gate node of the pass element. LDO regulators with feedback voltage sensing architecture operate over an input voltage range of 3.3V to 4.5V and have a load current of up to 200mA at an output voltage of 3V. According to the simulation result, when the load current is 200mA, it is 73mV under the undershoot condition and 61mV under the overshoot condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.56-65
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• 2006

The Quantum-dot Cellular Automata (QCA) can be considered as a candidate for the next generation digital logic implementation technology due to their small feature sizes and ultra low power consumption. Up to now, several designs using Uh technology have been proposed. However, we found not all of the designs function properly. Furthermore, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper, we show several critical vulnerabilities related to unbalanced input paths to QCA gates and sneak noise paths in QCA interconnect structures. In order to make up the vulnerabilities, a disciplinary guideline will be proposed. Also, we present a fast adder which has been designed by the discipline, and verified to be functional by the simulation.

• Journal of KIISE:Databases
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• v.30 no.6
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• pp.651-665
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• 2003

To reduce cache misses emerges as the most important issue in today's situation of main memory databases, in which CPU speeds have been increasing at 60% per year, and memory speeds at 10% per year. Recent researches have demonstrated that cache-conscious index structure such as the CR-tree outperforms the R-tree variants. Its search performance can be poor than the original R-tree, however, since it uses a lossy compression scheme. In this paper, we propose alternatively a cache-conscious version of the R-tree, which we call MR-tree. The MR-tree propagates node splits upward only if one of the internal nodes on the insertion path has empty room. Thus, the internal nodes of the MR-tree are almost 100% full. In case there is no empty room on the insertion path, a newly-created leaf simply becomes a child of the split leaf. The height of the MR-tree increases according to the sequence of inserting objects. Thus, the HeightBalance algorithm is executed when unbalanced heights of child nodes are detected. Additionally, we also propose the CCMR-tree in order to build a more cache-conscious MR-tree. Our experimental and analytical study shows that the two-dimensional MR-tree performs search up to 2.4times faster than the ordinary R-tree while maintaining slightly better update performance and using similar memory space.