• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Korean Electrochemical Society
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• v.12 no.2
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• pp.173-180
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• 2009

In order to develop a novel polymer electrolyte membrane for direct methanol fuel cell (DMFC), styrene monomer was graft-polymerized into poly(tetrafluoroethylene perfluoropropyl vinyl ether) (PFA) film followed by a sulfonation reaction. The graft polymerization was prepared by the $\Upsilon$-ray radiation-grafting method. Subsequently, sulfonation of the radiation-grafted film was carried out in a chlorosulfonic acid/1,2-dichloroethane (2 v/v%) solution. The chemical, physical, electrochemical and morphological properties of the radiation-grafted membranes (PFA-g-PSSA) were characterized by fourier transform infrared spectroscopy (FTIR) and scanning electron microscopy (SEM). The water uptake, ionic conductivity, and methanol permeability of the PFA-g-PSSA membrane were also measured. The cell performances of MEA prepared with the PFA-g-PSSA membranes were evaluated and the cell resistances were measured by an impedance analyzer. The MEA using PFA-g-PSSA membranes showed superior performance for DMFCs in comparison with the commercial Nafion 112 membrane.

• Journal of the Korean Society for Nondestructive Testing
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• v.30 no.2
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• pp.155-161
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• 2010

Recently, the electromagnetic techniques of the eddy current testing(ECT), alternating current field testing, magnetic flux leakage testing and remote field testing have been used as a nondestructive evaluation method based on the electromagnetic induction. The eddy current testing is now widely accepted as a NDE method for the heat exchanger tube in the electric power industry, chemical, shipbuilding, and military. The ECT system mainly consists of the synthesizer module, analog module, analog-to-digital converter, power supplier, and data acquisition and analysis program. In this study, the synthesizer module and the analog module which are essential to the ECT system were primarily developed. The developed ECT system is basically a multifrequency type which is able to inject the maximum four frequencies based on the frequency and time domain multiplexing method. Conclusively, we confirmed that the EC signal was processed appropriately in each circuit modules, and the Lissajous EC signal was displayed in the impedance plane.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.