• The Journal of Information Technology
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• v.1 no.2
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• pp.65-79
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• 1998

In this thesis, a buffer alloction and management algorithm is proposed in order to satisfy the QoS of CBR/VBR traffics incomming to ATM networks. Proposed traffic menagement algorithm is based on the route seperation mechanism that allocates buffers acoording to traffic characterics, and sets threshold to allocated buffers. We developed a cell scheduling algorithm and evaluated cell delay and loss probability characteristics according to incomming traffic classes. The cell scheduling algorithm uses buffer size thresholds to control overload traffic flow.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.10a
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• pp.174-177
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• 2006

본 논문에서는 리프팅 기반의 DWT 구조의 단점을 개선하고자 플립핑(Flipping)기법과 5 단 파이프라인 구조(5 Stage Pipeline)를 적용하여 임계경로가 획기적으로 줄어든 1 차원 DWT 구조를 제안하고 이를 활용하여 JPEG2000 표준의 손실 압축 모드에서 이용되는 9/7 필터계수의 2 차원 DWT 를 수행 할 수 있도록 열 방향 DWT 처리기를 설계하였다. 2 차원 DWT 는 1 차원 DWT 의 처리 결과에 대해 열상의 열(Column) 방향으로 2 차원 처리를 수행해야 하므로 1 차원 결과를 저장하기 위한 한 영상 사이즈 만큼의 메모리 버퍼를 필요로 한다. 기존 $N^2$이 필요하던 메모리 사이즈를 14N으로 줄인 2차원 구조를 제안한다.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.73-78
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• 2019

Due to frequent topology changes in wireless networks, inter-node link disconnection and path re-establishment occur, causing problems such as overloading control messages in the network. In this paper, to solve the problems such as link disconnection and control message overload, we perform path setup in three steps of the neighbor node discovery process, the route discovery process, and the route management process in the wireless network environment. The link stability value is calculated using the information of the routing table. Then, when the zone master monitors the calculated link value and becomes less than the threshold value, it predicts the link disconnection and performs the path reset to the corresponding transmitting and receiving node. The proposed scheme shows a performance improvement over the existing OLSR protocol in terms of data throughput, average path setup time, and data throughput depending on the speed of the mobile node as the number of mobile nodes changes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.39-47
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• 2010

This paper proposes a fully-utilized block-based 2D DWT architecture, which consists of four 1D DWT filters with two-channel QMF PR Lattice structure. For 100% hardware utilization, we propose a new method which processes four input values at the same time. On the contrary to the image-based 2D DWT which requires large memories, we propose a block-based 2D DWT so that we only need 2MN-3N of storages, where M and N stand for filter lengths and width of the image respectively. Furthermore, the proposed architecture processes in horizontal and vertical directions simultaneously so that it computes the DWT for an $N{\times}N$ image within a period of $N^2(1-2^{-2J})/3$. Compared to existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rate. However, the proposed architecture may suffer from the long critical path delay due to the cascaded lattices in 1D DWT filters. This problem can be mitigated by applying the pipeline technique with maximum four level. The proposed architecture has been designed with VerilogHDL and synthesized using DongbuAnam $0.18{\mu}m$ standard cell.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.41-49
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• 2010

This paper proposes a new high speed SHA-1 architecture using multiple unfolding and pre-computation techniques. We unfolds iterative hash operations to 2 continuos hash stage and reschedules computation timing. Then, the part of critical path is computed at the previous hash operation round and the rest is performed in the present round. These techniques reduce 3 additions to 2 additions on the critical path. It makes the maximum clock frequency of 118 MHz which provides throughput rate of 5.9 Gbps. The proposed architecture shows 26% higher throughput with a 32% smaller hardware size compared to other counterparts. This paper also introduces a analytical model of multiple SHA-1 architecture at the system level that maps a large input data on SHA-1 block in parallel. The model gives us the required number of SHA-1 blocks for a large multimedia data processing that it helps to make decision hardware configuration. The hs fospeed SHA-1 is useful to generate a condensed message and may strengthen the security of mobile communication and internet service.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.694-696
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• 1998

ILP마이크로세서를 위한 스테쥴링 과정에서 메모리 명령어가 프로그램의 임계 경로로에 존재할 경우에 이의 스케쥴링은 성능 향상에 중요한 문제 중에 하나이다. 메모리 명령어의 원활한 코드 이동을 위해서는 장애가 되는 명령어들의 메모리 주소간의 의존성의 분석을 필요로 한다. 본 논문에서는 컴파일 시간에 메모리 주소간의 의존성 분석을 통한 성능 향상도를 VLIW환경 하에서 비교한다. 실험결과. 컴파일 시간에 메모리 주소 모호성 제거기를 사용한 경우 16ALU프로세서에서 정수 벤치마크 프로그램에 대해서 기하 평균으로 약 3.6%의 성능 향상이 가능하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8C
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• pp.821-826
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• 2003

In this paper, constrained Remez exchange algorithm is proposed to reduce the critical path of an IIR filter. The proposed algorithm is based on Remez exchange algorithm and least squares method. By IIR filter design examples, it is shown that the proposed method can maximally increase speed by 20%.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.13-15
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• 2003

본 논문에서는 XML 문서의 자동변환을 위해 2단계의 상향식 매칭 방법을 제안한다. 제안된 방법은 단말 노드 사이의 유사도 비교를 통해 임계값을 넘는 후보 매칭집합을 결정하고, 단말노드가 포함되어 있는 경로의 유사도 비교를 통해 적절한 일대일 매칭을 추출한다. 특히, 노드 사이의 유사도 비교를 위해 축약어 사전, 일반 동의어 사전, 도메인 온톨로지를 적용한다. 실제 전자상거래용 XML 스키마를 대상으로 실험한 결과 제안된 방법은 평균적으로 97%의 정확률을 보였다.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.667-669
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• 2005

TCP Vegas나 FAST TCP는 RTT(Round Trip Time) 동안 실제 처리량(actual throughput)이 기대 처리량 (expected throughput)보다 특정 임계값보다 더 작으면 혼잡 상황으로 판단하고 송신측에서 내보내는 데이터 양을 감소시킴으로써 혼잡을 제어한다. 그러나 RTT 기반의 처리량(Throughput) 측정은 송수신 경로가 다를 경우 양방향 경로의 혼잡 상황을 구분하지 않는 문제점을 가지고 있다. 따라서 본 논문에서는 TCP Timestamp를 이용하여 양방향 혼잡 상황을 구분하여 혼잡을 제어하는 메커니즘을 제안한다. 그리고 제안한 방식에 대한 성능 분석을 위해 NS-2의 TCP Vegas를 수정하여 시뮬레이션한 결과를 제시한다.

• Journal of Korea Multimedia Society
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• v.2 no.2
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• pp.200-216
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• 1999

In this paper, we propose a BTPN (Beta-distributed Timed Petri Net) model which is not only an effective multimedia synchronization and authoring specification model, but also a direct control model for playout of a title. Methods of specification of relationships among all media objects in a title by using the BTPN structure and language, as well as methods of analysis of the BTPN by means of a Remaining Timed Reachability Graph and Timing diagram, are proposed. A concept of critical object path, coming from PERT/CPM, is useful for modeling the uncertainty of playout of a multimedia title and editing of title.