• The KIPS Transactions:PartA
• /
• v.9A no.4
• /
• pp.573-580
• /
• 2002

Reusing IPs requires interface protocol related tasks such as writing test benches and designing interface protocol conversion circuits, e.g. wrappers for IPs. The results of those tasks usually include IPC(interface protocol component)s for the corresponding IPs, similar to bus protocol components of the bus functional models. This paper proposes a methodology for the interface circuit design using synthesizable In that can be re-used. IPC recognizes or executes transactions over the given interface ports. So we present a transaction-oriented interface protocol description language, and a method to convert the description into an IPC in synthesizable VHDL code. With experiments, we show that the interface design using IPC does not cause significant area overhead compared with the interface design without IPC. The proposed IPC-based approach can be employed to reduce the interface design time since the designers can reuse IPCs without understanding the detailed interface protocols.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.2
• /
• pp.259-266
• /
• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.10 s.352
• /
• pp.34-44
• /
• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.14 no.3
• /
• pp.529-536
• /
• 2019

In order to apply a piezoelectric energy harvester to a smart sensor system, an energy harvest interface circuit including an AC-DC rectifier is required. In this paper, we compared the performance of full bridge rectifier, which is a typical energy harvester interface circuit, and synchronous piezoelectric energy harvest interface circuit by using board-level simulation. As a result, the output power of a synchronous electric charge extraction(: SECE) circuit is about four times larger than that of the full bridge rectifier, and there is little load variation. And a high voltage comparator, which is essential for the SECE circuit for the piezoelectric energy harvester with an output voltage of 40V or more, was designed using 0.35 um BCD process. The SECE circuit using the designed high-voltage comparator proved that the output power is 427 % higher than the FBR circuit.

• ETRI Journal
• /
• v.14 no.4
• /
• pp.194-209
• /
• 1992

애널로그 회로 시뮬레이터인 HSPICE에 대한 사용자 인터페이스 시스팀을 개발하였다. 이 시스팀은 HSPICE 가 탑재된 컴퓨터와 TCP/IP 네트워크로 연결된 시스팀에서 HSPICE를 사용할 수 있도록 하는 네트워크 인터페이스 기능과 HSPICE 출력 데이터를 실제 신호 파형으로 그래픽 처리해서 분석할 수 있게 하는 사용자 인터페이스 기능을 제공한다. HSPICE 사용자가 아닌 일반 SPICE 사용자들도 출력데이터를 HSPICE 의 Graph Data File의 형태로 변환시켜 주면 사용자 인터페이스 기능을 이용해서 출력 데이터의 그래픽 처리 및 분석이 가능하다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.669-673
• /
• 2004

인터넷의 사용이 증가, 네트워크 기술이 발달하면서 컴퓨터 및 하드웨어 장비는 고속화 대용량화, 소형화 추세로 가고 있고, 기존에 외부 인터페이스와의 데이터 송수신 또한 병렬 포트를 이용한 통신이 많았으나, 외부 장비의 소형화와 고속화 그리고 휴대화가 요구되면서 차츰 직렬 포트를 이용하여 적은 전송라인을 이용한 외부 장비와의 인터페이스가 요구 되게 되었다. 본 논문에서는 내부 모듈간의 인터페이스와 외부 장치와의 데이터 송/수신이 가능한 UART 인터페이스 모듈을 하드웨어 설계언어인 VHDL 언어를 이용하여 설계하였으며, FPGA 칩인 Xilinx(Spartan II) 데스트 보드에 다운로드하여 시뮬레이션 하였다. 또한 양방향성 공통 버스로의 인터페이스 회로 설계와 다른 클럭으로 동작하는 시스템과의 비동기 회로의 동작 메커니즘을 쉽게 설계하였고, 비동기 통신 기능에 있어서 실제로 사용이 가능하도록 설계하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.8A
• /
• pp.820-829
• /
• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Proceedings of the KAIS Fall Conference
• /
• 2002.05a
• /
• pp.215-217
• /
• 2002

본 논문에서는 CM-MVL(Current Mode Multi-Valued Logic)을 이용한 Host와 LCD Controller 간에 인터페이스 회로를 제안한다. 제안한 회로는 기존의 LVDS(Low Voltage Differential Signaling)과 TMDS(Transition Minimized Differential Signaling)와 같은 전류 특성을 가지며, 3비트 동시 전송이 가능하여 동일한 전송 속도 하에서 보다 많은 데이터를 전송할 수 있다. 그리고 전류에 의한 데이터 전송을 통하여 노이즈에 강한 특성을 나타낸다. 제안한 회로는 HSPICE 시뮬레이션을 통해서 회로의 동작을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.89-93
• /
• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.05a
• /
• pp.1065-1068
• /
• 2008

RFID를 이용한 화물추적시스템은 물류분야의 특성상 서로 다른 소속의 이 기종 간의 데이터의 인터페이스로 화물의 흐름을 체계화한다. 국내뿐 아니라 국제적으로도 여러 종류의 데이터를 인터페이스하고 있으며, 이 데이터들은 EDI 표준을 이용하여 다양한 환경의 시스템으로 인터페이스 되어 적용되고 있다. 하나의 물류흐름을 만들기 위하여 RFID를 이용한 데이터의 인터페이스가 이루어지다 보니 다양한 보안상의 문제를 유발시키고 있는 실정이다. 본 논문에서는 인공신경망 회로를 이용하여 이 기종 간의 EDI 데이터 인터페이스 시 발생할 수 있는 보안상의 취약점을 미리 파악하여 적절한 조치를 취할 수 있도록 방향을 제시하였다.