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http://dx.doi.org/10.6109/jkiice.2021.25.2.259

Implementation of FPGA Verification System with Slave FIFO Interface and FX3 USB 3 Bridge Chip  

Choi, Byeong-Yoon (Department of Computer Engineering, Dong-Eui University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.25, no.2, 2021 , pp. 259-266 More about this Journal
Abstract
USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.
Keywords
FPGA; Platform invoke; USB 3 Interface; Verification System;
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