• Journal of the Korea Convergence Society
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• v.8 no.8
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• pp.9-15
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• 2017

With the development of semiconductor integration technology, central processing units and storage devices have been miniaturized and performance has been rapidly developed, interconnection network technology is becoming a more important factor in terms of the performance of high performance computing system. In this paper, we analyze the trend of interconnection network technology used in high performance computing. Interconnect technology, which is the most widely used in the Supercomputer Top 500(2017. 06.), is an Infiniband. Recently, Ethernet is the second highest share after InfiniBand due to the emergence of 40/100Gbps Gigabit Ethernet technology. Gigabit Ethernet, where latency performance is lower than InfiniBand, is preferred in cost-effective medium-sized data centers. In addition, top-end HPC systems that demand high performance are devoting themselves from Ethernet and InfiniBand technologies and are attempting to maximize system performance by introducing their own interconnect networks. In the future, high-performance interconnects are expected to utilize silicon-based optical communication technology to exchange data with light.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.04a
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• pp.68-70
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• 2017

KISTI 슈퍼컴퓨터 4호기 Tachyon2는 SUN Blade 6275 시스템을 기반으로 구성된 초병렬 컴퓨팅 시스템으로 이론최고성능(Rpeak) 300TFlops를 보이고 있으며 3,200대의 컴퓨팅 노드와 인프라 노드로 구분된다. Tachyon2 시스템은 국내 산학연 연구자들을 위한 공공 목적의 시스템으로 만여 명의 사용자와 200여개의 기관이 사용 중에 있다. 이런 슈퍼컴퓨터와 같은 대형 HPC 환경에서는 대규모의 사용자 작업을 원활하게 수행하기 위해서는 IB의 안정성이 우선적으로 보장되어야 한다. 본 논문에서는 Tachyon2 시스템에서 발생하는 IB 상태를 파악하고 관리하기 위한 자동화 도구를 개발하였다. 이로써 인터커넥션의 상태를 주기적으로 모니터링 할 수 있고, 장애내역 또한 신속하게 파악할 수 있다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.3
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• pp.105-112
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• 2017

PCI Express is a bus technology that connects the processor and the peripheral I/O devices that widely used as an industry standard because it has the characteristics of high-speed, low power. In addition, PCI Express is system interconnect technology such as Ethernet and Infiniband used in high-performance computing and computer cluster. PGAS(partitioned global address space) programming model is often used to implement the one-sided RDMA(remote direct memory access) from multi-host systems, such as computer clusters. In this paper, we design and implement a OpenSHMEM API based on PCI Express maintaining the existing features of OpenSHMEM to implement RDMA based on PCI Express. We perform experiment with implemented OpenSHMEM API through a matrix multiplication example from system which PCs connected with NTB(non-transparent bridge) technology of PCI Express. The PCI Express interconnection network is currently very expensive and is not yet widely available to the general public. Nevertheless, we actually implemented and evaluated a PCI Express based interconnection network on the RDK evaluation board. In addition, we have implemented the OpenSHMEM software stack, which is of great interest recently.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.30-32
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• 1998

멀티프로세서 시스템을 설계할 경우에는 공유메모리 구조와 메시지 전달방법의 두 가지의 패러다임을 바탕으로 하게 된다. 데이터 분할과 동적 부하 분산 문제를 단순화시틸 수 있으며 확장성을 용이하게 지원하는 장점을 가지고 있는 공유메모리 구조의 멀티프로세서 시스템에서 각 프로세서가 자신의 전용 캐시를 가지는 경우에는 메인 메모리와 이러한 전용 캐시내에 존재하는 데이터사본간에 일관성 문제가 발생한다. 본 논문에서는 일관성 유지를 위해 제안되어 있는 여러 알고리즘 중 처리 노드와 고대역 저지연 인터커넥션 네트워크로 구성되는 공유메모리 구조의 멀티프로세서 프로토타입인 DASH 프로토콜을 지원하기 위한 전용 버스 시스템을 완전 개방형인 IEEE Futurebus+ 스탠다드에 준비하여 설계한 다음, 이 시스템이 DASH 프로토콜을 지원하려 캐시의 일관성을 유지하기 위해 필요한 각종 행동과 기존의 범용 버스 시스템이 수행하는 행동의 병렬 처리를 지원할 수 있음을 시뮬레이션으로 증명한다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1842-1850
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• 1997

This paper proposes a new rearrangeable algorithm in multistage reverse shuffle/exchange network. The best known lower bound of stages for rearrangeability in symmetric network is 2logN-1 stages. However, it has never been proved for nonsymmetric networks before. Currently, the best upper bound for the rearrangeability of a shuffle/exchange network in nonsymmetric network is 3logN-3 stages. We describe the rearrangeability of reverse shuffle/exchange multistage interconnection network on every arbitrary permutation with $N{\le}16$. This rearrangeability can be established by setting one more stages in the middle stage of the network to allow the reduced network to be topological equivalent to a class of rearrangeable networks. The results in this paper enable us to establish an upper bound, 2logN stages for rearrangeable reverse shuffle/exchange network with $N{\le}16$, and leads to the possibility of this bound when $N{\le}16$.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.68-75
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• 2016

As the number of cores and IPs increase in multiprocessor system-on-chip (MPSoC), network-on-chip (NoC) has emerged as a promising novel interconnection architecture for its parallelism and scalability. However, minimization of the latency in NoC with legacy bus IPs must be addressed. In this paper, we focus on the latency minimization problem in NoC which accommodates legacy bus protocol based IPs considering the trade-offs between hop counts and path collisions. To resolve this problem, we propose separated address/data network for independent address and data phases of bus protocol. Compared to Mesh and irregular topologies generated by TopGen, experimental results show that average latency and execution time are reduced by 19.46% and 10.55%, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11B
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• pp.946-955
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• 2004

It is shown that the do Bruijn graph (dBG) can be used as an architecture for interconnection network and a suitable structure for parallel computation. Recent works have classified dBG based routing algorithms into shortest path routing and fault tolerant routing but investigation into fault free shortest path (FFSP) on dBG has been non-existent. In addition, as the size of the network increase, more faults are to be expected and therefore shortest path dBG algorithms in fault free mode may not be suitable routing algorithms for real interconnection networks, which contain several failures. Furthermore, long fault free path may lead to high traffic, high delay time and low throughput. In this paper we investigate routing algorithms in the condition of existing failure, based on the Bidirectional do Bruijn graph (BdBG). Two FFSP routing algorithms are proposed. Then, the performances of the two algorithms are analyzed in terms of mean path lengths and discrete set mean sizes. Our study shows that the proposed algorithms can be one of the candidates for routing in real interconnection networks based on dBG.