• Title/Summary/Keyword: 이중 루프

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Example Development of Medical Equipment Applying Power Electronics Technique (전력전자 기술을 응용한 의료장비 개발 사례)

  • 고종선;이태훈;김영일;김규겸;박병림
    • The Transactions of the Korean Institute of Power Electronics
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    • v.7 no.6
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    • pp.524-530
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    • 2002
  • A control of the body posture and movement is maintained by the vestibular system, vision, and proprioceptors. Afferent signals from those receptors are transmitted to the vestibular nuclear complex, and the efferent signals from the vestibular nuclear complex control the eye movement and skeletal muscle contract. The postural disturbance caused by loss of the vestibular function results in nausea, vomiting, vertigo and loss of craving for life. The purpose of this study is to develop a off-vertical rotatory system for evaluating the function of semicircular canals and otolith organs, selectively, and visual stimulation system for- stimulation with horizontal, vortical and 3D patterns. The Off-vortical axis rotator is composed of a comportable chair, a DC servo-motor with reducer and a tilting table controlled by PMSM. And a double feedback loop system containing a velocity feedback loop and a position feedback loop is applied to the servo controlled rotatory chair system. Horizontal, vertical, and 3D patterns of the visual stimulation for applying head mounted display are developed. And wireless portable systems for optokinetic stimulation and recording system of the eye movement is also constructed. The gain, phase, and symmetry is obtained from analysis of the eye movement induced by vestibular and visual stimulation. Detailed data were described.

Adaptive Execution Techniques for Parallel Programs (병렬 프로그램의 적응형 실행 기법)

  • 이재진
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.8
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    • pp.421-431
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    • 2004
  • This paper presents adaptive execution techniques that determine whether parallelized loops are executed in parallel or sequentially in order to maximize performance. The adaptation and performance estimation algorithms are implemented in a compiler preprocessor. The preprocessor inserts code that automatically determines at compile-time or at run-time the way the parallelized loops are executed. Using a set of standard numerical applications written in Fortran77 and running them with our techniques on a distributed shared memory multiprocessor machine (SGI Origin2000), we obtain the performance of our techniques, on average, 26%, 20%, 16%, and 10% faster than the original parallel program on 32, 16, 8, and 4 processors, respectively. One of the applications runs even more than twice faster than its original parallel version on 32 processors.

Wide Range Analog Dual-Loop Delay-Locked Loop (광대역 아날로그 이중 루프 Delay-Locked Loop)

  • Lee, Seok-Ho;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.44 no.1
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    • pp.74-84
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    • 2007
  • This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

The Design of Resonator for Miniaturization of Magnetic Resonance Wireless Power Transfer System (자기공진형 무선전력전송 시스템의 소형화를 위한 공진기 설계)

  • Kang, Seok Hyon;Jung, Chang Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.2
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    • pp.163-169
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    • 2016
  • In this paper, we miniaturized the loop and coil in magnetic resonance wireless power transfer(MR-WPT) system for application to the small mobile device. The proposed disk type double coil resonator was designed to cause resonance at 6.87 MHz. It is composed of thin copper on both-side of acrylic substrate structured 2 mm width, 1 mm pitch and 8 turns. The outer radius of spiral coil pattern is 9 cm. And the proposed loop was made of the copper wire 5 mm diameter of cross-section. The size of loop is 10 cm diameter. For resonance at 6.87 MHz, the capacitor with 3,300 pF was connected in series on the loop. We rearranged the resonators and organized several WPT systems which is rearranged by resonators. The highest transfer efficiency of miniaturized WPT system was 35.67 %. This proposed design of spiral double coil will contribute to make resonator smaller for appling small and thin mobile device.

Dual-Mode Reference-less Clock Data Recovery Algorithm (이중 모드의 기준 클록을 사용하지 않는 클록 데이터 복원 회로 알고리즘)

  • Kwon, Ki-Won;Jin, Ja-Hoon;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.77-86
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    • 2016
  • This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

Research on the Development of the Supercritical CO2 Dual Brayton Cycle (초임계 이산화탄소 이중 브레이튼 사이클 개발 연구)

  • Baik, Young-Jin;Na, Sun Ik;Cho, Junhyun;Shin, Hyung-Ki;Lee, Gilbong
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.40 no.10
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    • pp.673-679
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    • 2016
  • Because of the growing interest in supercritical carbon dioxide power cycle technology owing to its potential enhancement in compactness and efficiency, supercritical carbon dioxide cycles have been studied in the fields of nuclear power, concentrated solar power (CSP), and fossil fuel power generation. This study introduces the current status of the research project on the supercritical carbon dioxide power cycle by Korea Institute of Energy Research (KIER). During the first phase of the project, the un-recuperated supercritical Brayton cycle test loop was built and tested. In phase two, researchers are designing and building a supercritical carbon dioxide dual Brayton cycle, which utilizes two turbines and two recuperators. Under the simulation condition considered in this study, it was confirmed that the design parameter has an optimal value for maximizing the net power in the supercritical carbon dioxide dual cycle.

Design of Wide - range Clock and Data Recovery Circuit based Dual-loop DLL using 2-step DPC (2-step DPC를 이용한 이중루프 DLL기반의 광대역 클록 데이터 복원회로 설계)

  • Jung, Ki-Sang;Kim, Kang-Jik;Ko, Gui-Han;Cho, Seong-Ik
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.61 no.2
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    • pp.324-328
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    • 2012
  • A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

Optimization of Control Parameters for Hydraulic Systems Using Genetic Algorithms (유전알고리듬을 이용한 유압시스템의 제어파라메터 최적화)

  • Hyeon, Jang-Hwan
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.21 no.9
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    • pp.1462-1469
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    • 1997
  • This study presents a genetic algorithm-based method for optimizing control parameters in fluid power systems. Genetic algorithms are general-purpose optimization methods based on natural evolution and genetics. A genetic algorithm seeks control parameters maximizing a measure that evaluates system performance. Five control gains of the PID-PD cascade controller fr an electrohydraulic speed control system with a variable displacement hydraulic motor are optimized using a genetic algorithm in the experiment. Optimized gains are confirmed by inspecting the fitness distribution which represents system performance in gain spaces. It is shown that optimization of the five gains by manual tuning should be a task of great difficulty and that a genetic algorithm is an efficient scheme giving economy of time and in labor in optimizing control parameters of fluid power systems.

Robust Control System of PMSM using Dual Adaptive Control Loop (이중 적응제어 루프를 이용한 영구자석 동기 전동기의 강인성 제어 시스템)

  • Yoon, Byung-Do;Kim, Yoon-Ho;Yoon, Myoung-Kyun;Kim, Cheol-Ho
    • Proceedings of the KIEE Conference
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    • 1991.11a
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    • pp.175-178
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    • 1991
  • The drive system of servo motor is requested to have robustness of disturbance and parameter variation. However, the dynamics of PMSM drive change significantly by forced disturbance and parameter variation. Moreover, the state error caused by them should be suppressed completely and rapidly. In this paper, the vector-control system of PMSM using dual adaptive control loop is investigated. In the proposed system, linear adaptive control loop rapidly recovers the state error caused by both disturbance and parameter variation. In the dual adaptive control loop, the inner loop reduces the system sensitivity of parameter variation and disturbance, and the outer loop suppresses the state error caused by them completely. The proposed servo system is verified through a computer simulations and experimental results.

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Position Control of Linear Synchronous Motor by Dual Learning (이중 학습에 의한 선형동기모터의 위치제어)

  • Park, Jung-Il;Suh, Sung-Ho;Ulugbek, Umirov
    • Journal of the Korean Society for Precision Engineering
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    • v.29 no.1
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    • pp.79-86
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    • 2012
  • This paper proposes PID and RIC (Robust Internal-loop Compensator) based motion controller using dual learning algorithm for position control of linear synchronous motor respectively. Its gains are auto-tuned by using two learning algorithms, reinforcement learning and neural network. The feedback controller gains are tuned by reinforcement learning, and then the feedforward controller gains are tuned by neural network. Experiments prove the validity of dual learning algorithm. The RIC controller has better performance than does the PID-feedforward controller in reducing tracking error and disturbance rejection. Neural network shows its ability to decrease tracking error and to reject disturbance in the stop range of the target position and home.