• Korean Journal of Optics and Photonics
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• v.19 no.3
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• pp.161-168
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• 2008

We propose a novel bistable nematic liquid crystal cell, which has a dual-frequency liquid crystal material and pixel-isolating polymer wall formed by an anisotropic phase separation of a mixture of liquid crystals and UV-curable pre-polymers. The proposed cell has two stable states of left- and right-handed ${\pi}$-twist. The switching between the two states is achieved by using a sequential waveform of low and high frequencies. A transmissive bistable liquid crystal display is designed, which achieves high contrast ratio by using the proposed cell and optical films.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.12 s.115
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• pp.1206-1211
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• 2006

In this paper, a Balun-BPF with the balun and BPF characteristics is proposed by using dual-mode ring resonator of $1{\lambda}$. We obtained the property of balun with the phase imbalance by symmetrically placing each output of ring resonator. The dual mode has been made by impedance difference between input and output lines. The fabricated Balun-BPF shows bandwidth of 40 MHz and insertion loss of 2.4 dB at a center frequency of 2.45 GHz. It shows the phase imbalance of $180{\sim}184$ degree and the magnitude imbalance of within 1 dB. The measured frequency responses agree well with simulated ones.

• Proceedings of the Optical Society of Korea Conference
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• 2003.07a
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• pp.238-239
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• 2003

2차원 슬랩 형태의 단일 결함 레이저는 낮은 발진 문턱값과 작은 모드 부피로 인해 문턱 없는 레이저의 동작 가능성, 광자 집적 회로에서의 광원 소자 등으로 각광을 받고 있다. 광결정은 결정 구조에 따라 삼각격자와 사각격자로 나눌 수 있는데, 특히 삼각격자의 경우 사각격자에 비해 밴드갭이 보다 넓은 주파수 영역에 걸쳐 나타나므로, 공진기와 도파로서의 응용에 더 적합한 소재로 연구되고 있다. 2차원 삼각구조 단일 결함 광결정은 60$^{\circ}$회전에 대하여 대칭성을 가지므로, 군론에 따라 기본적으로 60$^{\circ}$,120$^{\circ}$,180$^{\circ}$,360$^{\circ}$의 회전 대칭성을 가지고 있는 네 종류의 모드가 존재한다. (중략)

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.1
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• pp.46-52
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• 2009

This paper design QHA(quadrifilar helical antenna) to receive efficiently Satellite-Digital Multimedia Broadcasting video signal. It is designed as quadrifilar structure with phase variation $0^{\circ}C$, $90^{\circ}C$, $180^{\circ}C$, $270^{\circ}C$ to obtain circular polarization. Upper gap, turn number and height of QHA are varied to obtain optimization dimensions. Optimization dimensions are gap=2.2mm, turn number=0.9, height=42mm and input reflection coefficient is approximately -5.8dB. Designed QHA can be applied to Satellite-DMB terminal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.657-666
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• 2002

In this paper, a new broadband phase shifter to adjust the slope of dispersive phase characteristic for frequency of transmission network was proposed. The new fundamental network consists of a fixed main line with a length of λ/2 at the center frequency and two double stubs, each with a length of λ/8 at the center frequency, which are open and shorted, respectively, and which are shunted at the edge points of the main line. Characteristic impedances of the main line and two parallel double stubs are adjusted to produce a minimum phase error and to obtain an input and output match at the desired phase shift. Especially, the proposed structure is especially suitable for a broadband phase shifter with large phase shifts more than 90$^{\circ}$, and it is operated in the octave bandwidth. To verify the usefulness of a new broadband phase shifter, each 45$^{\circ}$-, 90$^{\circ}$-, 180$^{\circ}$-bit phase shifter and 3-bit phase shifter(45$^{\circ}$-phase step), which is cascaded in series, operated at the center frequency 3 GHz were designed, fabricated and experimented. The measured results were in very close agreement with the corresponding simulation results over the bandwidth of I/O impedance match and phase error for each phase shift.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.