• JOURNAL OF ELECTRICAL WORLD
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• no.12 s.96
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• pp.6-7
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• 1984

• JOURNAL OF ELECTRICAL WORLD
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• s.262
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• pp.20-30
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• 1998

• Korean Architects
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• no.4 s.300
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• pp.19-19
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• 1994

• Proceedings of the Korean Society of Food and Cookery Science Conference
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• 2003.05a
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• pp.93-93
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• 2003

보리가루를 이용한 중편 제조의 표준 확립을 위해 mesh, 수분량을 달리한 중편을 제조하여 보리증편 개발의 기초자료로 삼고자 하였다. 보리는 35mesh(A시료)ㆍ80 mesh(B시료), 재료의 비율은 보리시료 중량(15g)에 대하여 탁주 20％, 설탕 20％,소금 1.3％로 일정하게 하고, 수분은 110％, 130％, 150％로 첨가량을 조절하여 Rheometer (Compac-100, Japan)를 이용하여 경도, 점도를 측정하였다. 경도는 B시료가 A시료보다 부드럽게 각 시료는 수분함량이 높아질수록 부드럽게 나타났으며 점도는 B시료가 A시료보다 낮게 나타났다. (중략)

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.802-804
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• 2001

현재 산업 현장에서 사용되고 있는 산업용 감시카메라는 고정채널방식에 기반한 아날로그 카메라들이 대부분이며 하나의 모니터에 종속되어 사용되는 것이 일반적이다. 이로 인해 대규모의 산업용 감시 카메라를 보유한 대규모공장의 조업에 적잖은 비능률을 초래해 왔다. 본 논문에서는 현재 산업용 감시카메라들의 운영에 관한 문제점들을 들고 이를 극복할 수 있는 대안으로 IP기반의 디지털 카메라를 이용한 산업용 감시카메라의 네트워크 구성을 제안한다.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.943-946
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• 1999

In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm onstructs a bounded-skew tree(BST) in two steps:(ⅰ) a bottom-up phase to construct a binary tree of shortest-distance feasible regions which represent the loci of possible placements of clock entry points, and (ⅱ) a top-down phase to determine the exact locations of clock entry points. Experimental results show that our clock routing algorithm, named BST/DME, can produce a set of solutions with skew and wirelength trade-off.

• Proceedings of the Korean Environmental Sciences Society Conference
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• 2000.05a
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• pp.51-52
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• 2000

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.867-870
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• 1998

In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.345-348
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• 2000

In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.