• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.4
• /
• pp.129-133
• /
• 2020

In this paper, a temperature compensation circuit is presented in order to mitigate gain variability due to temperature in the W-band low-noise amplifier (LNA). The proposed cascode temperature compensation bias circuit automatically controls gate bias voltages of the common-source LNA in order to suppress variations of small-signal gain. The designed circuit was realized in a 100-nm GaAs pHEMT process. The simulated voltage gain of W-band LNA including the proposed bias circuit is >20 dB with gain variability less than ±0.8 dB in the range of temperatures between -35 to 71℃. We expect that the proposed circuit contributes to millimeter-wave receivers for stable performances in radar applications.

• Journal of IKEEE
• /
• v.7 no.1 s.12
• /
• pp.43-55
• /
• 2003

A degenerated differential pair has been widely used as a standard topology for digitally programmable CMOS VGAs. A variable degeneration resistor has been implemented using a resistor string or R-2R ladder with MOSFET switches. However, in the VGAs using these conventional methods, low-voltage and high-speed operation is very hard to achieve due to the dc voltage drop over the degeneration resistor. To overcome the problem a new variable degeneration resistor is proposed where the dc voltage drop is almost removed. The proposed gain control scheme makes it easy to implement a low-voltage and high-speed VGA. This paper describes the problems existed in conventional methods, the principle and advantages of the proposed scheme, and their performance comparison in detail. A CMOS VGA cell is designed using the proposed degeneration resistor. The 3dB bandwidths are greater than 650㎒ and the gain errors are less than 0.3dB in a gain control range from -12dB to +12dB in 6dB steps. It consumes 3.1㎃ from a 2.5V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.1
• /
• pp.77-83
• /
• 2011

In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.42 no.3 s.333
• /
• pp.1-8
• /
• 2005

In this paper, design and implement 60W Doherty power amplifiers for 3GPP repeater and base station transceiver system. Efficiency improvement and high power property of Doherty power amplifier is distinguishable; however implementation of assistance amplifer is difficult, though. To solve the problem, therefore, GCHD (Gate Control Hybrid Doherty) power amplifier is embodied to gate bias adjusament circuit of assistance amplifier to General Doherty power amplifier. Experiment result shows that $2.11\~2.17GHz$, 3GPP operating frequency band, with 62.55 dB gain, PEP output is 50,76 dBm, W-CDMA average power is 47.81 dBm, and -40.05 dBc ACLR characteristic in 5MHz offset frequency band. Each of the parameter satisfied amplifier specification which we want to design. Especially, GCHD power amplifier shows proper efficiency performance improvement in uniformity ACLR than general power amplifier.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11A
• /
• pp.902-911
• /
• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.3
• /
• pp.421-432
• /
• 2020

This paper proposes a 2-kW solid-state power amplifier (SSPA) developed by employing power amplifier pallets designed using gallium-nitride high electron mobility transistors, which is used in S-band military radars and to replace existing traveling-wave tube amplifier (TWTA). The SSPA consists of a high-power amplifier module, which combines eight power amplifier pallets, a drive amplifier module, a digital control module, and a power supply unit. First, the amplifier module and component were integrated into a small package to account for space limitations; next, an on-board harmonic filter was fabricated to reject spurious components; and finally, an auto gain control system was designed for various duty ratios because recent military radar systems are all active phase radars using the pulse operation mode. The developed SSPA exhibited a max gain of 48 dB and an output power ranging between 63-63.6 dBm at a frequency band of 3.1 to 3.5 GHz. The auto gain control function showed that the output power is regulated around 63 dBm despite the fluctuation of the input power from 15-20 dBm. Finally, reliability of the developed system was verified through a temperature environment test for nine hours at high (55 ℃) / low (-40℃) temperature profile in accordance with military standard 810. The developed SSPA show better performance such as light weight, high output, high gain, various safety function, low repair cost and short repair time than existing TWTA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.4 no.1
• /
• pp.77-88
• /
• 2000

In this paper, the 3-mode variable gain high power amplifier for a transmitter of INMARSAT-B operating at L-band(1626.5-1646.5 MHz) was developed. This SSPA can amplify 42 dBm in high power mode, 38 dBm in medium power mode and 36 dBm in low power mode for INMARSAT-B. The allowable errol sets +1 dBm as the upper limit and -2 dBm as the lower limit, respectively. To simplify the fabrication process, the whole system is designed by two parts composed of a driving amplifier and a high power amplifier. The HP's MGA-64135 and Motorola's MRF-6401 were used for driving amplifier, and the ERICSSON's PTE-10114 and PTF-10021 for the high power amplifier. The SSPA was fabricated by the RP circuits, the temperature compensation circuits and 3-mode variable gain control circuits and 20 dB parallel coupled-line directional coupler in aluminum housing. In addition, the gain control method was proposed by digital attenuator for 3-mode amplifier. Then il has been experimentally verified that the gain is controlled for single tone signal as well as two tone signals. In this case, the SSPA detects the output power by 20 dB parallel coupled-line directional coupler and phase non-splitter amplifier. The realized SSPA has 41.6 dB, 37.6 dB and 33.2 dB for small signal gain within 20 MHz bandwidth, and the VSWR of input and output port is less than 1.3:1. The minimum value of the 1 dB compression point gets more than 12 dBm for 3-mode variable gain high power amplifier. A typical two tone intermodulation point has 36.5 dBc maximum which is single carrier backed off 3 dB from 1 dB compression point. The maximum output power of 43 dBm was achieved at the 1636.5 MHz. These results reveal a high power of 20 Watt, which was the design target.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.1
• /
• pp.50-54
• /
• 2011

In this article, the linearity of single power amplifier is improved by suppress $2^{nd}$ and $3^{rd}$ harmonics at output port of high power amplifier and by cancelling of $3^{rd}$ IMD. The matching network in order to suppress harmonics consists of metamaterial like the CRLH. The $2^{nd}$ and $3^{rd}$ harmonics are suppressed over 27 dBc, respectively. A phase of generated $3^{rd}$ IMD at output of DPA (drive power amplifier) has changed in order to offset the $3^{rd}$ IMD of HPA (high power amplifier). The harmonics of the proposed PAM suppress over 6 dB than single HPA. The PAM has a 36.98 dBm of the output power, 21.6 dB of the power gain and 29.4 % of the PAE. The harmonics is a -53 dBc about PAM. This result indicate that a harmonic level is lower 20 dB than reference power amplifier.

• Journal of Korea Multimedia Society
• /
• v.10 no.1
• /
• pp.49-57
• /
• 2007

Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.68-74
• /
• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.