• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.728-736
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• 2007

The more improved the Internet and the information technology, the stronger cryptographic system is required which can satisfy the information security on the platform of personal hand-held devices or smart card system. This paper introduces a case study of designing an elliptic curve cryptographic processor of a high performance that can be suitably used in a wireless communicating device or in an embedded system. To design an efficient cryptographic system, we first analyzed the operation hierarchy of the elliptic curve cryptographic system and then implemented the system by adopting a serial cell multiplier and modified Euclid divider. Simulation result shows that the system was correctly designed and it can compute thousands of operations per a secdond.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.935-938
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• 2003

The performance of elliptic curve based on public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes a finite field multiplier and divider which is implemented using SystemC. Also this present an efficient hardware for performing the elliptic curve point multiplication using the polynomial basis representation. In order to improve the speed of the multiplier with as a little extra hardware as possible, adopted hybrid finite field multiplication and finite field divider.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.411-414
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• 2001

본 논문에서는 유한체 연산을 바탕으로 하는 공개키 암호화 프로세서를 위한 효율적인 곱셈기 구조를 제안한다. 제안된 곱셈기는 다항식으로 항이 모두 1인, AOP, 기약 다항식을 사용하였다. 제안된 구조는 LFSR 구조에 기반한 곱셈기 구조이다. VHDL 코드 시뮬레이션 결과 제안된 구조가 기존의 구조에 비해서 보다 효율적인 구조 복잡도를 가짐을 알 수 있었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.1
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• pp.53-60
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• 1996

오증 요소로부터 오류위치다항식의 계수를 계산함으로서 (23,12) Golay 부호를 복호할 수 있는 대수적 복호법이 최근 증명되었다. GF(2)상에서의 3중 오류정정 BCH부호의 복호법을 이 부호에 완벽하게 적용하여 해석하는 것을 소개한다. 그리고 GF(2)에 대한 최적의 정규기저를 구하여 이를 유한체 연산에 적용하며 단계별로 복호 회로의 구성을 제시한다. 이는 기존의 복호기보다 논리회로적으로 간단하며, 복호된 정보를 얻기까지 35번의 치환이 필요하다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.02a
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• pp.69-72
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• 2008

최근 PKI-less 공개키 암호 시스템에 대한 연구가 진척되면서, 페어링(Pairing) 기반의 암호 시스템이 주목을 받고 있다. 페어링 기반의 암호 시스템은 두 개의 타원 곡선 상의 점을 유한체의 값으로 보내는 양방향 선형성(Bilinearity)을 가지는 페어링 함수를 기반으로 구성되는 암호 시스템이다. 페어링 기반의 암호 시스템 구현을 위해서는 페어링 연산 알고리즘이 필수적이며, 효율적인 페어링 연산을 위한 많은 연구가 진행되고 있다. 이러한 페어링 알고리즘에도 기존의 타원곡선 스칼라곱 알고리즘에서 야기되었던 부채널 공격이 동일하게 적용되기 때문에, 안전한 페어링 알고리즘을 위해서는 부채널 공격에 대한 저항성을 갖는 알고리즘이 필요하다. 이에 본 논문에서는 부채널 공격에도 안전하면서 비교적 효율적인 이진 필드 상의 페어링 알고리즘을 제시한다. 본 페어링 알고리즘은 기존의 부체널 공격 저항성을 갖는 페어링 알고리즘 중 가장 효율적인 알고리즘에 비해 효율성이 17% 정도 향상되었다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.1
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• pp.81-88
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• 2002

For efficient implementation of scalar multiplication in Elliptic Curve Cryptosystems over Small Fields of Odd Characterist, robenius endomorphism is useful. We discuss new algorithm for multiplying points on Elliptic Curve Cryptosystems over Small ields. Our algorithm can reduce more the length of the Frobenius expansion than that of Smart.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.38-48
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• 2006

In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.